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Use always_inline in the MIPS support where applicable.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3375 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-10-09 03:39:58 +00:00
parent 6dab28d5b5
commit aa34373598
4 changed files with 28 additions and 28 deletions
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8
target-mips/exec.h
View File

@ -205,15 +205,15 @@ FOP_PROTO(le)
FOP_PROTO(ngt)
#undef FOP_PROTO
static inline void env_to_regs(void)
static always_inline void env_to_regs(void)
{
}
static inline void regs_to_env(void)
static always_inline void regs_to_env(void)
{
}
static inline int cpu_halted(CPUState *env)
static always_inline int cpu_halted(CPUState *env)
{
if (!env->halted)
return 0;
@ -225,7 +225,7 @@ static inline int cpu_halted(CPUState *env)
return EXCP_HALTED;
}
static inline void compute_hflags(CPUState *env)
static always_inline void compute_hflags(CPUState *env)
{
env->hflags &= ~(MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | MIPS_HFLAG_F64 |
MIPS_HFLAG_FPU | MIPS_HFLAG_UM);

4
target-mips/op.c
View File

@ -812,13 +812,13 @@ void op_msubu (void)
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
static inline uint64_t get_HILO (void)
static always_inline uint64_t get_HILO (void)
{
return ((uint64_t)env->HI[0][env->current_tc] << 32) |
((uint64_t)(uint32_t)env->LO[0][env->current_tc]);
}
static inline void set_HILO (uint64_t HILO)
static always_inline void set_HILO (uint64_t HILO)
{
env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF);
env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);

10
target-mips/op_helper.c
View File

@ -146,12 +146,12 @@ void do_drotrv (void)
/* 64 bits arithmetic for 32 bits hosts */
#if TARGET_LONG_BITS > HOST_LONG_BITS
static inline uint64_t get_HILO (void)
static always_inline uint64_t get_HILO (void)
{
return (env->HI[0][env->current_tc] << 32) | (uint32_t)env->LO[0][env->current_tc];
}
static inline void set_HILO (uint64_t HILO)
static always_inline void set_HILO (uint64_t HILO)
{
env->LO[0][env->current_tc] = (int32_t)HILO;
env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
@ -673,7 +673,7 @@ void do_ctc1 (int reg)
do_raise_exception(EXCP_FPE);
}
inline char ieee_ex_to_mips(char xcpt)
static always_inline char ieee_ex_to_mips(char xcpt)
{
return (xcpt & float_flag_inexact) >> 5 |
(xcpt & float_flag_underflow) >> 3 |
@ -682,7 +682,7 @@ inline char ieee_ex_to_mips(char xcpt)
(xcpt & float_flag_invalid) << 4;
}
inline char mips_ex_to_ieee(char xcpt)
static always_inline char mips_ex_to_ieee(char xcpt)
{
return (xcpt & FP_INEXACT) << 5 |
(xcpt & FP_UNDERFLOW) << 3 |
@ -691,7 +691,7 @@ inline char mips_ex_to_ieee(char xcpt)
(xcpt & FP_INVALID) >> 4;
}
inline void update_fcr31(void)
static always_inline void update_fcr31(void)
{
int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));

34
target-mips/translate.c
View File

@ -436,7 +436,7 @@ NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
}; \
static inline void func(int n) \
static always_inline void func(int n) \
{ \
NAME ## _table[n](); \
}
@ -470,7 +470,7 @@ NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
}; \
static inline void func(int n) \
static always_inline void func(int n) \
{ \
NAME ## _table[n](); \
}
@ -521,7 +521,7 @@ static GenOpFunc1 * gen_op_cmp ## type ## _ ## fmt ## _table[16] = { \
gen_op_cmp ## type ## _ ## fmt ## _le, \
gen_op_cmp ## type ## _ ## fmt ## _ngt, \
}; \
static inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
static always_inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
{ \
gen_op_cmp ## type ## _ ## fmt ## _table[n](cc); \
}
@ -636,7 +636,7 @@ do { \
glue(gen_op_store_fpr_, FTn)(Fn); \
} while (0)
static inline void gen_save_pc(target_ulong pc)
static always_inline void gen_save_pc(target_ulong pc)
{
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
if (pc == (int32_t)pc) {
@ -649,7 +649,7 @@ static inline void gen_save_pc(target_ulong pc)
#endif
}
static inline void gen_save_btarget(target_ulong btarget)
static always_inline void gen_save_btarget(target_ulong btarget)
{
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
if (btarget == (int32_t)btarget) {
@ -662,7 +662,7 @@ static inline void gen_save_btarget(target_ulong btarget)
#endif
}
static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
{
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
@ -694,7 +694,7 @@ static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
}
}
static inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
static always_inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
{
ctx->saved_hflags = ctx->hflags;
switch (ctx->hflags & MIPS_HFLAG_BMASK) {
@ -712,7 +712,7 @@ static inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
}
}
static inline void generate_exception_err (DisasContext *ctx, int excp, int err)
static always_inline void generate_exception_err (DisasContext *ctx, int excp, int err)
{
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM)
@ -726,24 +726,24 @@ static inline void generate_exception_err (DisasContext *ctx, int excp, int err)
ctx->bstate = BS_EXCP;
}
static inline void generate_exception (DisasContext *ctx, int excp)
static always_inline void generate_exception (DisasContext *ctx, int excp)
{
generate_exception_err (ctx, excp, 0);
}
static inline void check_cp0_enabled(DisasContext *ctx)
static always_inline void check_cp0_enabled(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
generate_exception_err(ctx, EXCP_CpU, 1);
}
static inline void check_cp1_enabled(DisasContext *ctx)
static always_inline void check_cp1_enabled(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
generate_exception_err(ctx, EXCP_CpU, 1);
}
static inline void check_cp1_64bitmode(DisasContext *ctx)
static always_inline void check_cp1_64bitmode(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64)))
generate_exception(ctx, EXCP_RI);
@ -768,7 +768,7 @@ void check_cp1_registers(DisasContext *ctx, int regs)
/* This code generates a "reserved instruction" exception if the
CPU does not support the instruction set corresponding to flags. */
static inline void check_insn(CPUState *env, DisasContext *ctx, int flags)
static always_inline void check_insn(CPUState *env, DisasContext *ctx, int flags)
{
if (unlikely(!(env->insn_flags & flags)))
generate_exception(ctx, EXCP_RI);
@ -776,7 +776,7 @@ static inline void check_insn(CPUState *env, DisasContext *ctx, int flags)
/* This code generates a "reserved instruction" exception if the
CPU is not MIPS MT capable. */
static inline void check_mips_mt(CPUState *env, DisasContext *ctx)
static always_inline void check_mips_mt(CPUState *env, DisasContext *ctx)
{
if (unlikely(!(env->CP0_Config3 & (1 << CP0C3_MT))))
generate_exception(ctx, EXCP_RI);
@ -784,7 +784,7 @@ static inline void check_mips_mt(CPUState *env, DisasContext *ctx)
/* This code generates a "reserved instruction" exception if 64-bit
instructions are not enabled. */
static inline void check_mips_64(DisasContext *ctx)
static always_inline void check_mips_64(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
generate_exception(ctx, EXCP_RI);
@ -1634,7 +1634,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
ctx->bstate = BS_STOP;
}
static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
static always_inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
TranslationBlock *tb;
tb = ctx->tb;
@ -6477,7 +6477,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
}
}
static inline int
static always_inline int
gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
int search_pc)
{