target-tilegx: Handle simple logical operations
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
444e06b172
commit
a9fdfc7e7b
@ -106,9 +106,64 @@ static void gen_exception(DisasContext *dc, TileExcp num)
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dc->exit_tb = true;
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}
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static bool check_gr(DisasContext *dc, uint8_t reg)
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{
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if (likely(reg < TILEGX_R_COUNT)) {
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return true;
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}
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switch (reg) {
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case TILEGX_R_SN:
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case TILEGX_R_ZERO:
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break;
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case TILEGX_R_IDN0:
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case TILEGX_R_IDN1:
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gen_exception(dc, TILEGX_EXCP_REG_IDN_ACCESS);
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break;
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case TILEGX_R_UDN0:
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case TILEGX_R_UDN1:
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case TILEGX_R_UDN2:
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case TILEGX_R_UDN3:
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gen_exception(dc, TILEGX_EXCP_REG_UDN_ACCESS);
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break;
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default:
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g_assert_not_reached();
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}
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return false;
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}
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static TCGv load_zero(DisasContext *dc)
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{
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if (TCGV_IS_UNUSED_I64(dc->zero)) {
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dc->zero = tcg_const_i64(0);
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}
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return dc->zero;
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}
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static TCGv load_gr(DisasContext *dc, unsigned reg)
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{
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if (check_gr(dc, reg)) {
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return cpu_regs[reg];
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}
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return load_zero(dc);
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}
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static TCGv dest_gr(DisasContext *dc, unsigned reg)
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{
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int n;
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/* Skip the result, mark the exception if necessary, and continue */
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check_gr(dc, reg);
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n = dc->num_wb++;
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dc->wb[n].reg = reg;
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return dc->wb[n].val = tcg_temp_new_i64();
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}
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static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
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unsigned dest, unsigned srca)
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{
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TCGv tdest, tsrca;
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const char *mnemonic;
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/* Eliminate nops before doing anything else. */
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@ -132,6 +187,9 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
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return TILEGX_EXCP_NONE;
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}
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tdest = dest_gr(dc, dest);
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tsrca = load_gr(dc, srca);
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switch (opext) {
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case OE_RR_X0(CNTLZ):
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case OE_RR_Y0(CNTLZ):
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@ -180,8 +238,12 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
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case OE_RR_Y0(PCNT):
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case OE_RR_X0(REVBITS):
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case OE_RR_Y0(REVBITS):
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return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
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case OE_RR_X0(REVBYTES):
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case OE_RR_Y0(REVBYTES):
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tcg_gen_bswap64_tl(tdest, tsrca);
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mnemonic = "revbytes";
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break;
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case OE_RR_X1(SWINT0):
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case OE_RR_X1(SWINT1):
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case OE_RR_X1(SWINT2):
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@ -207,6 +269,9 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
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static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
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unsigned dest, unsigned srca, unsigned srcb)
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{
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TCGv tdest = dest_gr(dc, dest);
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TCGv tsrca = load_gr(dc, srca);
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TCGv tsrcb = load_gr(dc, srcb);
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const char *mnemonic;
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switch (opext) {
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@ -220,10 +285,14 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
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case OE_RRR(ADD, 0, X1):
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case OE_RRR(ADD, 0, Y0):
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case OE_RRR(ADD, 0, Y1):
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return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
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case OE_RRR(AND, 0, X0):
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case OE_RRR(AND, 0, X1):
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case OE_RRR(AND, 5, Y0):
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case OE_RRR(AND, 5, Y1):
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tcg_gen_and_tl(tdest, tsrca, tsrcb);
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mnemonic = "and";
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break;
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case OE_RRR(CMOVEQZ, 0, X0):
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case OE_RRR(CMOVEQZ, 4, Y0):
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case OE_RRR(CMOVNEZ, 0, X0):
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@ -334,14 +403,21 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
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case OE_RRR(MZ, 0, X1):
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case OE_RRR(MZ, 4, Y0):
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case OE_RRR(MZ, 4, Y1):
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return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
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case OE_RRR(NOR, 0, X0):
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case OE_RRR(NOR, 0, X1):
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case OE_RRR(NOR, 5, Y0):
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case OE_RRR(NOR, 5, Y1):
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tcg_gen_nor_tl(tdest, tsrca, tsrcb);
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mnemonic = "nor";
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break;
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case OE_RRR(OR, 0, X0):
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case OE_RRR(OR, 0, X1):
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case OE_RRR(OR, 5, Y0):
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case OE_RRR(OR, 5, Y1):
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tcg_gen_or_tl(tdest, tsrca, tsrcb);
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mnemonic = "or";
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break;
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case OE_RRR(ROTL, 0, X0):
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case OE_RRR(ROTL, 0, X1):
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case OE_RRR(ROTL, 6, Y0):
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@ -539,10 +615,14 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
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case OE_RRR(V4SUBSC, 0, X1):
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case OE_RRR(V4SUB, 0, X0):
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case OE_RRR(V4SUB, 0, X1):
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return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
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case OE_RRR(XOR, 0, X0):
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case OE_RRR(XOR, 0, X1):
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case OE_RRR(XOR, 5, Y0):
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case OE_RRR(XOR, 5, Y1):
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tcg_gen_xor_tl(tdest, tsrca, tsrcb);
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mnemonic = "xor";
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break;
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default:
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return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
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}
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@ -555,6 +635,8 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
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static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
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unsigned dest, unsigned srca, int imm)
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{
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TCGv tdest = dest_gr(dc, dest);
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TCGv tsrca = load_gr(dc, srca);
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const char *mnemonic;
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switch (opext) {
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@ -562,8 +644,14 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
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case OE_IM(ADDI, X1):
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case OE_IM(ADDXI, X0):
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case OE_IM(ADDXI, X1):
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return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
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case OE(ANDI_OPCODE_Y0, 0, Y0):
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case OE(ANDI_OPCODE_Y1, 0, Y1):
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case OE_IM(ANDI, X0):
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case OE_IM(ANDI, X1):
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tcg_gen_andi_tl(tdest, tsrca, imm);
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mnemonic = "andi";
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break;
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case OE_IM(CMPEQI, X0):
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case OE_IM(CMPEQI, X1):
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case OE_IM(CMPLTSI, X0):
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@ -587,8 +675,12 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
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case OE_IM(LDNA_ADD, X1):
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case OE_IM(MFSPR, X1):
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case OE_IM(MTSPR, X1):
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return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
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case OE_IM(ORI, X0):
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case OE_IM(ORI, X1):
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tcg_gen_ori_tl(tdest, tsrca, imm);
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mnemonic = "ori";
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break;
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case OE_IM(ST1_ADD, X1):
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case OE_IM(ST2_ADD, X1):
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case OE_IM(ST4_ADD, X1):
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@ -621,8 +713,12 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
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case OE_IM(V2MAXSI, X1):
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case OE_IM(V2MINSI, X0):
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case OE_IM(V2MINSI, X1):
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return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
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case OE_IM(XORI, X0):
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case OE_IM(XORI, X1):
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tcg_gen_xori_tl(tdest, tsrca, imm);
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mnemonic = "xori";
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break;
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case OE_SH(ROTLI, X0):
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case OE_SH(ROTLI, X1):
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@ -665,8 +761,6 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
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case OE(ADDXI_OPCODE_Y1, 0, Y1):
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case OE(ADDXLI_OPCODE_X0, 0, X0):
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case OE(ADDXLI_OPCODE_X1, 0, X1):
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case OE(ANDI_OPCODE_Y0, 0, Y0):
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case OE(ANDI_OPCODE_Y1, 0, Y1):
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case OE(CMPEQI_OPCODE_Y0, 0, Y0):
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case OE(CMPEQI_OPCODE_Y1, 0, Y1):
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case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
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@ -1057,7 +1151,6 @@ static inline void gen_intermediate_code_internal(TileGXCPU *cpu,
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dc->jmp.cond = TCG_COND_NEVER;
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TCGV_UNUSED_I64(dc->jmp.dest);
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TCGV_UNUSED_I64(dc->jmp.val1);
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TCGV_UNUSED_I64(dc->jmp.val2);
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TCGV_UNUSED_I64(dc->zero);
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
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