mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target/mips: Convert MSA SHF opcode to decodetree

Browse Source 
Convert the SHF opcode (Immediate Set Shuffle Elements) to decodetree.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-12-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-10-19 09:54:17 +02:00
parent 4701d23aef
commit a9e1795833
2 changed files with 22 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
target/mips/tcg/msa.decode
View File

@ -26,6 +26,7 @@
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i
@i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i
@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi
@bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=%bit_df m=%bit_m
@ -38,6 +39,8 @@ BZ 010001 110 .. ..... ................ @bz
BNZ 010001 111 .. ..... ................ @bz
{
SHF 011110 .. ........ ..... ..... 000010 @i8_df
ADDVI 011110 000 .. ..... ..... ..... 000110 @u5
SUBVI 011110 001 .. ..... ..... ..... 000110 @u5
MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5

36
target/mips/tcg/msa_translate.c
View File

@ -60,13 +60,10 @@ enum {
/* I8 instruction */
OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00,
OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
OPC_SHF_B = (0x0 << 24) | OPC_MSA_I8_02,
OPC_ORI_B = (0x1 << 24) | OPC_MSA_I8_00,
OPC_BMZI_B = (0x1 << 24) | OPC_MSA_I8_01,
OPC_SHF_H = (0x1 << 24) | OPC_MSA_I8_02,
OPC_NORI_B = (0x2 << 24) | OPC_MSA_I8_00,
OPC_BSELI_B = (0x2 << 24) | OPC_MSA_I8_01,
OPC_SHF_W = (0x2 << 24) | OPC_MSA_I8_02,
OPC_XORI_B = (0x3 << 24) | OPC_MSA_I8_00,
/* VEC/2R/2RF instruction */
@ -465,20 +462,6 @@ static void gen_msa_i8(DisasContext *ctx)
case OPC_BSELI_B:
gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8);
break;
case OPC_SHF_B:
case OPC_SHF_H:
case OPC_SHF_W:
{
uint8_t df = (ctx->opcode >> 24) & 0x3;
if (df == DF_DOUBLE) {
gen_reserved_instruction(ctx);
} else {
TCGv_i32 tdf = tcg_const_i32(df);
gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8);
tcg_temp_free_i32(tdf);
}
}
break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
@ -490,6 +473,25 @@ static void gen_msa_i8(DisasContext *ctx)
tcg_temp_free_i32(ti8);
}
static bool trans_SHF(DisasContext *ctx, arg_msa_i *a)
{
if (a->df == DF_DOUBLE) {
return false;
}
if (!check_msa_enabled(ctx)) {
return true;
}
gen_helper_msa_shf_df(cpu_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
tcg_constant_i32(a->sa));
return true;
}
static bool trans_msa_i5(DisasContext *ctx, arg_msa_i *a,
gen_helper_piiii *gen_msa_i5)
{