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MIPS patches queue

Browse Source 
A bunch of cleanups from various people.
 
 - Improved GT64120 on big-endian hosts
 - GT64120 north bridge and MC146818 RTC devices are now target independent
 - Bonito64 north bridge converted to 3-phase reset API
 - PCI refactors around PIIX devices
 - Support for nanoMIPS in bootloader generator API
 - New YAMON Malta Avocado test
 - Removal of 'trap and emulate' KVM support
 - System-specific QMP commands restricted to system emulation
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Merge tag 'mips-20230113' of https://github.com/philmd/qemu into staging

MIPS patches queue

A bunch of cleanups from various people.

- Improved GT64120 on big-endian hosts
- GT64120 north bridge and MC146818 RTC devices are now target independent
- Bonito64 north bridge converted to 3-phase reset API
- PCI refactors around PIIX devices
- Support for nanoMIPS in bootloader generator API
- New YAMON Malta Avocado test
- Removal of 'trap and emulate' KVM support
- System-specific QMP commands restricted to system emulation

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# gpg: Signature made Fri 13 Jan 2023 15:35:28 GMT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'mips-20230113' of https://github.com/philmd/qemu: (46 commits)
  scripts/git.orderfile: Display MAINTAINERS changes first
  target/mips: Restrict 'qapi-commands-machine.h' to system emulation
  hw/mips/boston: Rename MachineState 'mc' pointer to 'ms'
  hw/pci-host/bonito: Declare TYPE_BONITO_PCI_HOST_BRIDGE in header
  hw/pci-host/bonito: Use 'bonito_pci' for PCI function #0 code
  hw/pci-host/bonito: Use 'bonito_host' for PCI host bridge code
  hw/pci-host/bonito: Convert to 3-phase reset
  softmmu/rtc: Emit warning when using driftfix=slew on systems without mc146818
  hw/rtc/mc146818rtc: Make the mc146818 RTC device target independent
  hw/core/qdev-properties-system: Allow the 'slew' policy only on x86
  hw/intc: Extract the IRQ counting functions into a separate file
  hw/intc/i8259: Make using the isa_pic singleton more type-safe
  hw/usb/hcd-uhci: Introduce TYPE_ defines for device models
  hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig
  hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific
  hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific
  hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs()
  hw/pci/pci_host: Trace config accesses on unexisting functions
  mips: Always include nanomips disassembler
  mips: Remove support for trap and emulate KVM
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-01-16 11:24:11 +00:00
commit a8d6abe129
62 changed files with 693 additions and 625 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
MAINTAINERS
View File

@ -1249,7 +1249,7 @@ S: Odd Fixes
F: hw/isa/piix4.c
F: hw/acpi/piix4.c
F: hw/mips/malta.c
F: hw/mips/gt64xxx_pci.c
F: hw/pci-host/gt64120.c
F: include/hw/southbridge/piix.h
F: tests/avocado/linux_ssh_mips_malta.py
F: tests/avocado/machine_mips_malta.py
@ -1270,6 +1270,7 @@ F: hw/isa/vt82c686.c
F: hw/pci-host/bonito.c
F: hw/usb/vt82c686-uhci-pci.c
F: include/hw/isa/vt82c686.h
F: include/hw/pci-host/bonito.h
F: tests/avocado/machine_mips_fuloong2e.py
Loongson-3 virtual platforms

3
configs/devices/mips-softmmu/common.mak
View File

@ -17,14 +17,11 @@ CONFIG_I8254=y
CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI_PIIX4=y
CONFIG_I8257=y
CONFIG_PIIX4=y
CONFIG_IDE_ISA=y
CONFIG_PFLASH_CFI01=y
CONFIG_I8259=y
CONFIG_MC146818RTC=y
CONFIG_EMPTY_SLOT=y
CONFIG_MIPS_CPS=y
CONFIG_MIPS_ITU=y
CONFIG_MALTA=y

3
disas/meson.build
View File

@ -4,8 +4,7 @@ common_ss.add(when: 'CONFIG_HEXAGON_DIS', if_true: files('hexagon.c'))
common_ss.add(when: 'CONFIG_HPPA_DIS', if_true: files('hppa.c'))
common_ss.add(when: 'CONFIG_M68K_DIS', if_true: files('m68k.c'))
common_ss.add(when: 'CONFIG_MICROBLAZE_DIS', if_true: files('microblaze.c'))
common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c'))
common_ss.add(when: 'CONFIG_NANOMIPS_DIS', if_true: files('nanomips.c'))
common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c', 'nanomips.c'))
common_ss.add(when: 'CONFIG_NIOS2_DIS', if_true: files('nios2.c'))
common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files('riscv.c'))
common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c'))

9
docs/about/deprecated.rst
View File

@ -171,15 +171,6 @@ accepted incorrect commands will return an error. Users should make sure that
all arguments passed to ``device_add`` are consistent with the documented
property types.
System accelerators
-------------------
MIPS ``Trap-and-Emul`` KVM support (since 6.0)
''''''''''''''''''''''''''''''''''''''''''''''
The MIPS ``Trap-and-Emul`` KVM host and guest support has been removed
from Linux upstream kernel, declare it deprecated.
Host Architectures
------------------

9
docs/about/removed-features.rst
View File

@ -652,6 +652,15 @@ Userspace local APIC with KVM (x86, removed 8.0)
a local APIC. The ``split`` setting is supported, as is using ``-M
kernel-irqchip=off`` when the CPU does not have a local APIC.
System accelerators
-------------------
MIPS "Trap-and-Emulate" KVM support (removed in 8.0)
''''''''''''''''''''''''''''''''''''''''''''''''''''
The MIPS "Trap-and-Emulate" KVM host and guest support was removed
from Linux in 2021, and is not supported anymore by QEMU either.
System emulator machines
------------------------

28
hw/core/qdev-properties-system.c
View File

@ -33,6 +33,7 @@
#include "net/net.h"
#include "hw/pci/pci.h"
#include "hw/pci/pcie.h"
#include "hw/i386/x86.h"
#include "util/block-helpers.h"
static bool check_prop_still_unset(Object *obj, const char *name,
@ -558,13 +559,38 @@ void qdev_set_nic_properties(DeviceState *dev, NICInfo *nd)
/* --- lost tick policy --- */
static void qdev_propinfo_set_losttickpolicy(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
{
Property *prop = opaque;
int *ptr = object_field_prop_ptr(obj, prop);
int value;
if (!visit_type_enum(v, name, &value, prop->info->enum_table, errp)) {
return;
}
if (value == LOST_TICK_POLICY_SLEW) {
MachineState *ms = MACHINE(qdev_get_machine());
if (!object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) {
error_setg(errp,
"the 'slew' policy is only available for x86 machines");
return;
}
}
*ptr = value;
}
QEMU_BUILD_BUG_ON(sizeof(LostTickPolicy) != sizeof(int));
const PropertyInfo qdev_prop_losttickpolicy = {
.name = "LostTickPolicy",
.enum_table = &LostTickPolicy_lookup,
.get = qdev_propinfo_get_enum,
.set = qdev_propinfo_set_enum,
.set = qdev_propinfo_set_losttickpolicy,
.set_default_value = qdev_propinfo_set_default_value_enum,
};

4
hw/i386/kvm/i8259.c
View File

@ -14,7 +14,7 @@
#include "hw/isa/i8259_internal.h"
#include "hw/intc/i8259.h"
#include "qemu/module.h"
#include "hw/i386/apic_internal.h"
#include "hw/intc/kvm_irqcount.h"
#include "hw/irq.h"
#include "sysemu/kvm.h"
#include "qom/object.h"
@ -117,7 +117,7 @@ static void kvm_pic_set_irq(void *opaque, int irq, int level)
pic_stat_update_irq(irq, level);
delivered = kvm_set_irq(kvm_state, irq, level);
apic_report_irq_delivered(delivered);
kvm_report_irq_delivered(delivered);
}
static void kvm_pic_realize(DeviceState *dev, Error **errp)

4
hw/i386/kvm/ioapic.c
View File

@ -15,7 +15,7 @@
#include "hw/i386/x86.h"
#include "hw/qdev-properties.h"
#include "hw/i386/ioapic_internal.h"
#include "hw/i386/apic_internal.h"
#include "hw/intc/kvm_irqcount.h"
#include "sysemu/kvm.h"
/* PC Utility function */
@ -116,7 +116,7 @@ static void kvm_ioapic_set_irq(void *opaque, int irq, int level)
ioapic_stat_update_irq(common, irq, level);
delivered = kvm_set_irq(kvm_state, s->kvm_gsi_base + irq, level);
apic_report_irq_delivered(delivered);
kvm_report_irq_delivered(delivered);
}
static void kvm_ioapic_realize(DeviceState *dev, Error **errp)

18
hw/i386/pc_piix.c
View File

@ -47,9 +47,11 @@
#include "hw/sysbus.h"
#include "hw/i2c/smbus_eeprom.h"
#include "hw/xen/xen-x86.h"
#include "hw/xen/xen.h"
#include "exec/memory.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/piix4.h"
#include "hw/usb/hcd-uhci.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/xen.h"
@ -73,6 +75,17 @@ static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
#endif
/*
* Return the global irq number corresponding to a given device irq
* pin. We could also use the bus number to have a more precise mapping.
*/
static int pc_pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
{
int slot_addend;
slot_addend = PCI_SLOT(pci_dev->devfn) - 1;
return (pci_intx + slot_addend) & 3;
}
/* PC hardware initialisation */
static void pc_init1(MachineState *machine,
const char *host_type, const char *pci_type)
@ -216,6 +229,9 @@ static void pc_init1(MachineState *machine,
x86ms->below_4g_mem_size,
x86ms->above_4g_mem_size,
pci_memory, ram_memory);
pci_bus_map_irqs(pci_bus,
xen_enabled() ? xen_pci_slot_get_pirq
: pc_pci_slot_get_pirq);
pcms->bus = pci_bus;
pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, type);
@ -290,7 +306,7 @@ static void pc_init1(MachineState *machine,
#endif
if (pcmc->pci_enabled && machine_usb(machine)) {
pci_create_simple(pci_bus, piix3_devfn + 2, "piix3-usb-uhci");
pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI);
}
if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {

17
hw/i386/pc_q35.c
View File

@ -48,6 +48,7 @@
#include "hw/ide/pci.h"
#include "hw/ide/ahci.h"
#include "hw/usb.h"
#include "hw/usb/hcd-uhci.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/numa.h"
@ -65,15 +66,15 @@ struct ehci_companions {
};
static const struct ehci_companions ich9_1d[] = {
{ .name = "ich9-usb-uhci1", .func = 0, .port = 0 },
{ .name = "ich9-usb-uhci2", .func = 1, .port = 2 },
{ .name = "ich9-usb-uhci3", .func = 2, .port = 4 },
{ .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 },
{ .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 },
{ .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 },
};
static const struct ehci_companions ich9_1a[] = {
{ .name = "ich9-usb-uhci4", .func = 0, .port = 0 },
{ .name = "ich9-usb-uhci5", .func = 1, .port = 2 },
{ .name = "ich9-usb-uhci6", .func = 2, .port = 4 },
{ .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 },
{ .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 },
{ .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 },
};
static int ehci_create_ich9_with_companions(PCIBus *bus, int slot)
@ -268,8 +269,8 @@ static void pc_q35_init(MachineState *machine)
for (i = 0; i < GSI_NUM_PINS; i++) {
qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
}
pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
ICH9_LPC_NB_PIRQS);
pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc, ICH9_LPC_NB_PIRQS);
pci_bus_map_irqs(host_bus, ich9_lpc_map_irq);
pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
isa_bus = ich9_lpc->isa_bus;

3
hw/intc/apic.c
View File

@ -22,6 +22,7 @@
#include "hw/i386/apic.h"
#include "hw/i386/ioapic.h"
#include "hw/intc/i8259.h"
#include "hw/intc/kvm_irqcount.h"
#include "hw/pci/msi.h"
#include "qemu/host-utils.h"
#include "sysemu/kvm.h"
@ -399,7 +400,7 @@ void apic_poll_irq(DeviceState *dev)
static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode)
{
apic_report_irq_delivered(!apic_get_bit(s->irr, vector_num));
kvm_report_irq_delivered(!apic_get_bit(s->irr, vector_num));
apic_set_bit(s->irr, vector_num);
if (trigger_mode)

30
hw/intc/apic_common.c
View File

@ -25,6 +25,7 @@
#include "qapi/visitor.h"
#include "hw/i386/apic.h"
#include "hw/i386/apic_internal.h"
#include "hw/intc/kvm_irqcount.h"
#include "trace.h"
#include "hw/boards.h"
#include "sysemu/hax.h"
@ -33,7 +34,6 @@
#include "hw/sysbus.h"
#include "migration/vmstate.h"
static int apic_irq_delivered;
bool apic_report_tpr_access;
void cpu_set_apic_base(DeviceState *dev, uint64_t val)
@ -122,32 +122,6 @@ void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
}
void apic_report_irq_delivered(int delivered)
{
apic_irq_delivered += delivered;
trace_apic_report_irq_delivered(apic_irq_delivered);
}
void apic_reset_irq_delivered(void)
{
/* Copy this into a local variable to encourage gcc to emit a plain
* register for a sys/sdt.h marker. For details on this workaround, see:
* https://sourceware.org/bugzilla/show_bug.cgi?id=13296
*/
volatile int a_i_d = apic_irq_delivered;
trace_apic_reset_irq_delivered(a_i_d);
apic_irq_delivered = 0;
}
int apic_get_irq_delivered(void)
{
trace_apic_get_irq_delivered(apic_irq_delivered);
return apic_irq_delivered;
}
void apic_deliver_nmi(DeviceState *dev)
{
APICCommonState *s = APIC_COMMON(dev);
@ -272,7 +246,7 @@ static void apic_reset_common(DeviceState *dev)
s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;
s->id = s->initial_apic_id;
apic_reset_irq_delivered();
kvm_reset_irq_delivered();
s->vapic_paddr = 0;
info->vapic_base_update(s);

11
hw/intc/i8259.c
View File

@ -55,7 +55,7 @@ struct PICClass {
#ifdef DEBUG_IRQ_LATENCY
static int64_t irq_time[16];
#endif
DeviceState *isa_pic;
PICCommonState *isa_pic;
static PICCommonState *slave_pic;
/* return the highest priority found in mask (highest = smallest
@ -173,9 +173,8 @@ static void pic_intack(PICCommonState *s, int irq)
pic_update_irq(s);
}
int pic_read_irq(DeviceState *d)
int pic_read_irq(PICCommonState *s)
{
PICCommonState *s = PIC_COMMON(d);
int irq, intno;
irq = pic_get_irq(s);
@ -354,10 +353,8 @@ static uint64_t pic_ioport_read(void *opaque, hwaddr addr,
return ret;
}
int pic_get_output(DeviceState *d)
int pic_get_output(PICCommonState *s)
{
PICCommonState *s = PIC_COMMON(d);
return (pic_get_irq(s) >= 0);
}
@ -426,7 +423,7 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq)
irq_set[i] = qdev_get_gpio_in(dev, i);
}
isa_pic = dev;
isa_pic = PIC_COMMON(dev);
isadev = i8259_init_chip(TYPE_I8259, bus, false);
dev = DEVICE(isadev);

49
hw/intc/kvm_irqcount.c Normal file
View File

@ -0,0 +1,49 @@
/*
* KVM PIC functions for counting the delivered IRQs.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>
*/
#include "qemu/osdep.h"
#include "hw/intc/kvm_irqcount.h"
#include "trace.h"
static int kvm_irq_delivered;
void kvm_report_irq_delivered(int delivered)
{
kvm_irq_delivered += delivered;
trace_kvm_report_irq_delivered(kvm_irq_delivered);
}
void kvm_reset_irq_delivered(void)
{
/*
* Copy this into a local variable to encourage gcc to emit a plain
* register for a sys/sdt.h marker. For details on this workaround, see:
* https://sourceware.org/bugzilla/show_bug.cgi?id=13296
*/
volatile int k_i_d = kvm_irq_delivered;
trace_kvm_reset_irq_delivered(k_i_d);
kvm_irq_delivered = 0;
}
int kvm_get_irq_delivered(void)
{
trace_kvm_get_irq_delivered(kvm_irq_delivered);
return kvm_irq_delivered;
}

6
hw/intc/meson.build
View File

@ -25,6 +25,12 @@ softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_intc.c'))
softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-ipi.c'))
softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-intc.c'))
if config_all_devices.has_key('CONFIG_APIC') or \
config_all_devices.has_key('CONFIG_I8259') or \
config_all_devices.has_key('CONFIG_MC146818RTC')
softmmu_ss.add(files('kvm_irqcount.c'))
endif
specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))
specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c'))

9
hw/intc/trace-events
View File

@ -10,10 +10,6 @@ pic_ioport_read(bool master, uint64_t addr, int val) "master %d addr 0x%"PRIx64"
# apic_common.c
cpu_set_apic_base(uint64_t val) "0x%016"PRIx64
cpu_get_apic_base(uint64_t val) "0x%016"PRIx64
# coalescing
apic_report_irq_delivered(int apic_irq_delivered) "coalescing %d"
apic_reset_irq_delivered(int apic_irq_delivered) "old coalescing %d"
apic_get_irq_delivered(int apic_irq_delivered) "returning coalescing %d"
# apic.c
apic_local_deliver(int vector, uint32_t lvt) "vector %d delivery mode %d"
@ -30,6 +26,11 @@ ioapic_mem_read(uint8_t addr, uint8_t regsel, uint8_t size, uint32_t val) "ioapi
ioapic_mem_write(uint8_t addr, uint8_t regsel, uint8_t size, uint32_t val) "ioapic mem write addr 0x%"PRIx8" regsel: 0x%"PRIx8" size 0x%"PRIx8" val 0x%"PRIx32
ioapic_set_irq(int vector, int level) "vector: %d level: %d"
# kvm_irqcount.c
kvm_report_irq_delivered(int irq_delivered) "coalescing %d"
kvm_reset_irq_delivered(int irq_delivered) "old coalescing %d"
kvm_get_irq_delivered(int irq_delivered) "returning coalescing %d"
# slavio_intctl.c
slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = 0x%x"
slavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) "write cpu %d reg 0x%"PRIx64" = 0x%x"

17
hw/isa/piix3.c
View File

@ -79,17 +79,6 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
piix3_set_irq_level(piix3, pirq, level);
}
/*
* Return the global irq number corresponding to a given device irq
* pin. We could also use the bus number to have a more precise mapping.
*/
static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
{
int slot_addend;
slot_addend = PCI_SLOT(pci_dev->devfn) - 1;
return (pci_intx + slot_addend) & 3;
}
static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
{
PIIX3State *piix3 = opaque;
@ -384,8 +373,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
return;
}
pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
piix3, PIIX_NUM_PIRQS);
pci_bus_irqs(pci_bus, piix3_set_irq, piix3, PIIX_NUM_PIRQS);
pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
}
@ -420,8 +408,7 @@ static void piix3_xen_realize(PCIDevice *dev, Error **errp)
* connected to the IOAPIC directly.
* These additional routes can be discovered through ACPI.
*/
pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
piix3, XEN_PIIX_NUM_PIRQS);
pci_bus_irqs(pci_bus, xen_piix3_set_irq, piix3, XEN_PIIX_NUM_PIRQS);
}
static void piix3_xen_class_init(ObjectClass *klass, void *data)

37
hw/isa/piix4.c
View File

@ -79,31 +79,6 @@ static void piix4_set_irq(void *opaque, int irq_num, int level)
}
}
static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
{
int slot;
slot = PCI_SLOT(pci_dev->devfn);
switch (slot) {
/* PIIX4 USB */
case 10:
return 3;
/* AMD 79C973 Ethernet */
case 11:
return 1;
/* Crystal 4281 Sound */
case 12:
return 2;
/* PCI slot 1 to 4 */
case 18 ... 21:
return ((slot - 18) + irq_num) & 0x03;
/* Unknown device, don't do any translation */
default:
return irq_num;
}
}
static void piix4_isa_reset(DeviceState *dev)
{
PIIX4State *d = PIIX4_PCI_DEVICE(dev);
@ -116,10 +91,10 @@ static void piix4_isa_reset(DeviceState *dev)
pci_conf[0x4c] = 0x4d;
pci_conf[0x4e] = 0x03;
pci_conf[0x4f] = 0x00;
pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
pci_conf[0x60] = 0x80;
pci_conf[0x61] = 0x80;
pci_conf[0x62] = 0x80;
pci_conf[0x63] = 0x80;
pci_conf[0x69] = 0x02;
pci_conf[0x70] = 0x80;
pci_conf[0x76] = 0x0c;
@ -271,7 +246,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
}
qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]);
pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS);
}
static void piix4_init(Object *obj)
@ -280,7 +255,7 @@ static void piix4_init(Object *obj)
object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE);
object_initialize_child(obj, "uhci", &s->uhci, "piix4-usb-uhci");
object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI);
object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM);
qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100);

2
hw/mips/Kconfig
View File

@ -1,6 +1,8 @@
config MALTA
bool
select GT64120
select ISA_SUPERIO
select PIIX4
config MIPSSIM
bool

141
hw/mips/bootloader.c
View File

@ -54,17 +54,37 @@ static bool bootcpu_supports_isa(uint64_t isa_mask)
return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask);
}
/* Base types */
static void bl_gen_nop(uint32_t **p)
static void st_nm32_p(void **ptr, uint32_t insn)
{
stl_p(*p, 0);
*p = *p + 1;
uint16_t *p = *ptr;
stw_p(p, insn >> 16);
p++;
stw_p(p, insn >> 0);
p++;
*ptr = p;
}
static void bl_gen_r_type(uint32_t **p, uint8_t opcode,
/* Base types */
static void bl_gen_nop(void **ptr)
{
if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
st_nm32_p(ptr, 0x8000c000);
} else {
uint32_t *p = *ptr;
stl_p(p, 0);
p++;
*ptr = p;
}
}
static void bl_gen_r_type(void **ptr, uint8_t opcode,
bl_reg rs, bl_reg rt, bl_reg rd,
uint8_t shift, uint8_t funct)
{
uint32_t *p = *ptr;
uint32_t insn = 0;
insn = deposit32(insn, 26, 6, opcode);
@ -74,13 +94,16 @@ static void bl_gen_r_type(uint32_t **p, uint8_t opcode,
insn = deposit32(insn, 6, 5, shift);
insn = deposit32(insn, 0, 6, funct);
stl_p(*p, insn);
*p = *p + 1;
stl_p(p, insn);
p++;
*ptr = p;
}
static void bl_gen_i_type(uint32_t **p, uint8_t opcode,
static void bl_gen_i_type(void **ptr, uint8_t opcode,
bl_reg rs, bl_reg rt, uint16_t imm)
{
uint32_t *p = *ptr;
uint32_t insn = 0;
insn = deposit32(insn, 26, 6, opcode);
@ -88,12 +111,14 @@ static void bl_gen_i_type(uint32_t **p, uint8_t opcode,
insn = deposit32(insn, 16, 5, rt);
insn = deposit32(insn, 0, 16, imm);
stl_p(*p, insn);
*p = *p + 1;
stl_p(p, insn);
p++;
*ptr = p;
}
/* Single instructions */
static void bl_gen_dsll(uint32_t **p, bl_reg rd, bl_reg rt, uint8_t sa)
static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa)
{
if (bootcpu_supports_isa(ISA_MIPS3)) {
bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38);
@ -102,28 +127,83 @@ static void bl_gen_dsll(uint32_t **p, bl_reg rd, bl_reg rt, uint8_t sa)
}
}
static void bl_gen_jalr(uint32_t **p, bl_reg rs)
static void bl_gen_jalr(void **p, bl_reg rs)
{
bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
uint32_t insn = 0;
insn = deposit32(insn, 26, 6, 0b010010); /* JALRC */
insn = deposit32(insn, 21, 5, BL_REG_RA);
insn = deposit32(insn, 16, 5, rs);
st_nm32_p(p, insn);
} else {
bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
}
}
static void bl_gen_lui(uint32_t **p, bl_reg rt, uint16_t imm)
static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20)
{
uint32_t insn = 0;
assert(extract32(imm20, 0, 20) == imm20);
insn = deposit32(insn, 26, 6, 0b111000);
insn = deposit32(insn, 21, 5, rt);
insn = deposit32(insn, 12, 9, extract32(imm20, 0, 9));
insn = deposit32(insn, 2, 10, extract32(imm20, 9, 10));
insn = deposit32(insn, 0, 1, sextract32(imm20, 19, 1));
st_nm32_p(ptr, insn);
}
static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm)
{
/* R6: It's a alias of AUI with RS = 0 */
bl_gen_i_type(p, 0x0f, 0, rt, imm);
}
static void bl_gen_ori(uint32_t **p, bl_reg rt, bl_reg rs, uint16_t imm)
static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_reg rs, uint16_t imm12)
{
uint32_t insn = 0;
assert(extract32(imm12, 0, 12) == imm12);
insn = deposit32(insn, 26, 6, 0b100000);
insn = deposit32(insn, 21, 5, rt);
insn = deposit32(insn, 16, 5, rs);
insn = deposit32(insn, 0, 12, imm12);
st_nm32_p(ptr, insn);
}
static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
{
bl_gen_i_type(p, 0x0d, rs, rt, imm);
}
static void bl_gen_sw(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12)
{
bl_gen_i_type(p, 0x2b, base, rt, offset);
uint32_t insn = 0;
assert(extract32(ofs12, 0, 12) == ofs12);
insn = deposit32(insn, 26, 6, 0b100001);
insn = deposit32(insn, 21, 5, rt);
insn = deposit32(insn, 16, 5, rs);
insn = deposit32(insn, 12, 4, 0b1001);
insn = deposit32(insn, 0, 12, ofs12);
st_nm32_p(ptr, insn);
}
static void bl_gen_sd(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
{
if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
bl_gen_sw_nm(p, rt, base, offset);
} else {
bl_gen_i_type(p, 0x2b, base, rt, offset);
}
}
static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
{
if (bootcpu_supports_isa(ISA_MIPS3)) {
bl_gen_i_type(p, 0x3f, base, rt, offset);
@ -133,13 +213,18 @@ static void bl_gen_sd(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
}
/* Pseudo instructions */
static void bl_gen_li(uint32_t **p, bl_reg rt, uint32_t imm)
static void bl_gen_li(void **p, bl_reg rt, uint32_t imm)
{
bl_gen_lui(p, rt, extract32(imm, 16, 16));
bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
bl_gen_lui_nm(p, rt, extract32(imm, 12, 20));
bl_gen_ori_nm(p, rt, rt, extract32(imm, 0, 12));
} else {
bl_gen_lui(p, rt, extract32(imm, 16, 16));
bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
}
}
static void bl_gen_dli(uint32_t **p, bl_reg rt, uint64_t imm)
static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm)
{
bl_gen_li(p, rt, extract64(imm, 32, 32));
bl_gen_dsll(p, rt, rt, 16);
@ -148,7 +233,7 @@ static void bl_gen_dli(uint32_t **p, bl_reg rt, uint64_t imm)
bl_gen_ori(p, rt, rt, extract64(imm, 0, 16));
}
static void bl_gen_load_ulong(uint32_t **p, bl_reg rt, target_ulong imm)
static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm)
{
if (bootcpu_supports_isa(ISA_MIPS3)) {
bl_gen_dli(p, rt, imm); /* 64bit */
@ -158,14 +243,14 @@ static void bl_gen_load_ulong(uint32_t **p, bl_reg rt, target_ulong imm)
}
/* Helpers */
void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr)
void bl_gen_jump_to(void **p, target_ulong jump_addr)
{
bl_gen_load_ulong(p, BL_REG_T9, jump_addr);
bl_gen_jalr(p, BL_REG_T9);
bl_gen_nop(p); /* delay slot */
}
void bl_gen_jump_kernel(uint32_t **p,
void bl_gen_jump_kernel(void **p,
bool set_sp, target_ulong sp,
bool set_a0, target_ulong a0,
bool set_a1, target_ulong a1,
@ -192,7 +277,7 @@ void bl_gen_jump_kernel(uint32_t **p,
bl_gen_jump_to(p, kernel_addr);
}
void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val)
void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val)
{
bl_gen_load_ulong(p, BL_REG_K0, val);
bl_gen_load_ulong(p, BL_REG_K1, addr);
@ -203,14 +288,14 @@ void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val)
}
}
void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val)
void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val)
{
bl_gen_li(p, BL_REG_K0, val);
bl_gen_load_ulong(p, BL_REG_K1, addr);
bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0);
}
void bl_gen_write_u64(uint32_t **p, target_ulong addr, uint64_t val)
void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val)
{
bl_gen_dli(p, BL_REG_K0, val);
bl_gen_load_ulong(p, BL_REG_K1, addr);

6
hw/mips/boston.c
View File

@ -323,7 +323,7 @@ static void boston_register_types(void)
}
type_init(boston_register_types)
static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr)
static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr)
{
uint64_t regaddr;
@ -515,7 +515,7 @@ static const void *create_fdt(BostonState *s,
{
void *fdt;
int cpu;
MachineState *mc = s->mach;
MachineState *ms = s->mach;
uint32_t platreg_ph, gic_ph, clk_ph;
char *name, *gic_name, *platreg_name, *stdout_name;
static const char * const syscon_compat[2] = {
@ -542,7 +542,7 @@ static const void *create_fdt(BostonState *s,
qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
name = g_strdup_printf("/cpus/cpu@%d", cpu);
qemu_fdt_add_subnode(fdt, name);
qemu_fdt_setprop_string(fdt, name, "compatible", "img,mips");

2
hw/mips/fuloong2e.c
View File

@ -179,7 +179,7 @@ static void write_bootloader(CPUMIPSState *env, uint8_t *base,
/* Second part of the bootloader */
p = (uint32_t *)(base + 0x040);
bl_gen_jump_kernel(&p,
bl_gen_jump_kernel((void **)&p,
true, ENVP_VADDR - 64,
true, 2, true, ENVP_VADDR,
true, ENVP_VADDR + 8,

403
hw/mips/malta.c
View File

@ -39,6 +39,7 @@
#include "hw/mips/bootloader.h"
#include "hw/mips/cpudevs.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
#include "qemu/log.h"
#include "hw/mips/bios.h"
#include "hw/ide/pci.h"
@ -53,11 +54,12 @@
#include "sysemu/runstate.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/misc/empty_slot.h"
#include "sysemu/kvm.h"
#include "semihosting/semihost.h"
#include "hw/mips/cps.h"
#include "hw/qdev-clock.h"
#include "target/mips/internal.h"
#include "trace.h"
#define ENVP_PADDR 0x2000
#define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
@ -71,6 +73,8 @@
#define FLASH_SIZE 0x400000
#define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0)
typedef struct {
MemoryRegion iomem;
MemoryRegion iomem_lo; /* 0 - 0x900 */
@ -106,11 +110,10 @@ static struct _loaderparams {
} loaderparams;
/* Malta FPGA */
static void malta_fpga_update_display(void *opaque)
static void malta_fpga_update_display_leds(MaltaFPGAState *s)
{
char leds_text[9];
int i;
MaltaFPGAState *s = opaque;
for (i = 7 ; i >= 0 ; i--) {
if (s->leds & (1 << i)) {
@ -121,8 +124,14 @@ static void malta_fpga_update_display(void *opaque)
}
leds_text[8] = '\0';
trace_malta_fpga_leds(leds_text);
qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
leds_text);
}
static void malta_fpga_update_display_ascii(MaltaFPGAState *s)
{
trace_malta_fpga_display(s->display_text);
qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
s->display_text);
}
@ -457,13 +466,13 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
/* LEDBAR Register */
case 0x00408:
s->leds = val & 0xff;
malta_fpga_update_display(s);
malta_fpga_update_display_leds(s);
break;
/* ASCIIWORD Register */
case 0x00410:
snprintf(s->display_text, 9, "%08X", (uint32_t)val);
malta_fpga_update_display(s);
malta_fpga_update_display_ascii(s);
break;
/* ASCIIPOS0 to ASCIIPOS7 Registers */
@ -476,7 +485,7 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
case 0x00448:
case 0x00450:
s->display_text[(saddr - 0x00418) >> 3] = (char) val;
malta_fpga_update_display(s);
malta_fpga_update_display_ascii(s);
break;
/* SOFTRES Register */
@ -611,6 +620,78 @@ static void network_init(PCIBus *pci_bus)
}
}
static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr,
uint64_t kernel_entry)
{
static const char pci_pins_cfg[PCI_NUM_PINS] = {
10, 10, 11, 11 /* PIIX IRQRC[A:D] */
};
/* Bus endianess is always reversed */
#if TARGET_BIG_ENDIAN
#define cpu_to_gt32 cpu_to_le32
#else
#define cpu_to_gt32 cpu_to_be32
#endif
/* setup MEM-to-PCI0 mapping as done by YAMON */
/* move GT64120 registers from 0x14000000 to 0x1be00000 */
bl_gen_write_u32(p, /* GT_ISD */
cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
cpu_to_gt32(0x1be00000 << 3));
/* setup PCI0 io window to 0x18000000-0x181fffff */
bl_gen_write_u32(p, /* GT_PCI0IOLD */
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
cpu_to_gt32(0x18000000 << 3));
bl_gen_write_u32(p, /* GT_PCI0IOHD */
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
cpu_to_gt32(0x08000000 << 3));
/* setup PCI0 mem windows */
bl_gen_write_u32(p, /* GT_PCI0M0LD */
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
cpu_to_gt32(0x10000000 << 3));
bl_gen_write_u32(p, /* GT_PCI0M0HD */
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
cpu_to_gt32(0x07e00000 << 3));
bl_gen_write_u32(p, /* GT_PCI0M1LD */
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
cpu_to_gt32(0x18200000 << 3));
bl_gen_write_u32(p, /* GT_PCI0M1HD */
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
cpu_to_gt32(0x0bc00000 << 3));
#undef cpu_to_gt32
/*
* The PIIX ISA bridge is on PCI bus 0 dev 10 func 0.
* Load the PIIX IRQC[A:D] routing config address, then
* write routing configuration to the config data register.
*/
bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8),
tswap32((1 << 31) /* ConfigEn */
| PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8
| PIIX_PIRQCA));
bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc),
tswap32(ldl_be_p(pci_pins_cfg)));
bl_gen_jump_kernel(p,
true, ENVP_VADDR - 64,
/*
* If semihosting is used, arguments have already
* been passed, so we preserve $a0.
*/
!semihosting_get_argc(), 2,
true, ENVP_VADDR,
true, ENVP_VADDR + 8,
true, loaderparams.ram_low_size,
kernel_entry);
}
static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
uint64_t kernel_entry)
{
@ -619,11 +700,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
/* Small bootloader */
p = (uint16_t *)base;
#define NM_HI1(VAL) (((VAL) >> 16) & 0x1f)
#define NM_HI2(VAL) \
(((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
#define NM_LO(VAL) ((VAL) & 0xfff)
stw_p(p++, 0x2800); stw_p(p++, 0x001c);
/* bc to_here */
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
@ -642,175 +718,8 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
/* nop */
/* to_here: */
if (semihosting_get_argc()) {
/* Preserve a0 content as arguments have been passed */
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
/* nop */
} else {
stw_p(p++, 0x0080); stw_p(p++, 0x0002);
/* li a0,2 */
}
stw_p(p++, 0xe3a0 | NM_HI1(ENVP_VADDR - 64));
stw_p(p++, NM_HI2(ENVP_VADDR - 64));
/* lui sp,%hi(ENVP_VADDR - 64) */
stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_VADDR - 64));
/* ori sp,sp,%lo(ENVP_VADDR - 64) */
stw_p(p++, 0xe0a0 | NM_HI1(ENVP_VADDR));
stw_p(p++, NM_HI2(ENVP_VADDR));
/* lui a1,%hi(ENVP_VADDR) */
stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_VADDR));
/* ori a1,a1,%lo(ENVP_VADDR) */
stw_p(p++, 0xe0c0 | NM_HI1(ENVP_VADDR + 8));
stw_p(p++, NM_HI2(ENVP_VADDR + 8));
/* lui a2,%hi(ENVP_VADDR + 8) */
stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_VADDR + 8));
/* ori a2,a2,%lo(ENVP_VADDR + 8) */
stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size));
stw_p(p++, NM_HI2(loaderparams.ram_low_size));
/* lui a3,%hi(loaderparams.ram_low_size) */
stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
/* ori a3,a3,%lo(loaderparams.ram_low_size) */
/*
* Load BAR registers as done by YAMON:
*
* - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
* - set up PCI0 MEM0 at 0x10000000, size 0x8000000
* - set up PCI0 MEM1 at 0x18200000, size 0xbe00000
*
*/
stw_p(p++, 0xe040); stw_p(p++, 0x0681);
/* lui t1, %hi(0xb4000000) */
#if TARGET_BIG_ENDIAN
stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
/* lui t0, %hi(0xdf000000) */
/* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c) */
stw_p(p++, 0x8422); stw_p(p++, 0x9068);
/* sw t0, 0x68(t1) */
stw_p(p++, 0xe040); stw_p(p++, 0x077d);
/* lui t1, %hi(0xbbe00000) */
stw_p(p++, 0xe020); stw_p(p++, 0x0801);
/* lui t0, %hi(0xc0000000) */
/* 0x48 corresponds to GT_PCI0IOLD */
stw_p(p++, 0x8422); stw_p(p++, 0x9048);
/* sw t0, 0x48(t1) */
stw_p(p++, 0xe020); stw_p(p++, 0x0800);
/* lui t0, %hi(0x40000000) */
/* 0x50 corresponds to GT_PCI0IOHD */
stw_p(p++, 0x8422); stw_p(p++, 0x9050);
/* sw t0, 0x50(t1) */
stw_p(p++, 0xe020); stw_p(p++, 0x0001);
/* lui t0, %hi(0x80000000) */
/* 0x58 corresponds to GT_PCI0M0LD */
stw_p(p++, 0x8422); stw_p(p++, 0x9058);
/* sw t0, 0x58(t1) */
stw_p(p++, 0xe020); stw_p(p++, 0x07e0);
/* lui t0, %hi(0x3f000000) */
/* 0x60 corresponds to GT_PCI0M0HD */
stw_p(p++, 0x8422); stw_p(p++, 0x9060);
/* sw t0, 0x60(t1) */
stw_p(p++, 0xe020); stw_p(p++, 0x0821);
/* lui t0, %hi(0xc1000000) */
/* 0x80 corresponds to GT_PCI0M1LD */
stw_p(p++, 0x8422); stw_p(p++, 0x9080);
/* sw t0, 0x80(t1) */
stw_p(p++, 0xe020); stw_p(p++, 0x0bc0);
/* lui t0, %hi(0x5e000000) */
#else
stw_p(p++, 0x0020); stw_p(p++, 0x00df);
/* addiu[32] t0, $0, 0xdf */
/* 0x68 corresponds to GT_ISD */
stw_p(p++, 0x8422); stw_p(p++, 0x9068);
/* sw t0, 0x68(t1) */
/* Use kseg2 remapped address 0x1be00000 */
stw_p(p++, 0xe040); stw_p(p++, 0x077d);
/* lui t1, %hi(0xbbe00000) */
stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
/* addiu[32] t0, $0, 0xc0 */
/* 0x48 corresponds to GT_PCI0IOLD */
stw_p(p++, 0x8422); stw_p(p++, 0x9048);
/* sw t0, 0x48(t1) */
stw_p(p++, 0x0020); stw_p(p++, 0x0040);
/* addiu[32] t0, $0, 0x40 */
/* 0x50 corresponds to GT_PCI0IOHD */
stw_p(p++, 0x8422); stw_p(p++, 0x9050);
/* sw t0, 0x50(t1) */
stw_p(p++, 0x0020); stw_p(p++, 0x0080);
/* addiu[32] t0, $0, 0x80 */
/* 0x58 corresponds to GT_PCI0M0LD */
stw_p(p++, 0x8422); stw_p(p++, 0x9058);
/* sw t0, 0x58(t1) */
stw_p(p++, 0x0020); stw_p(p++, 0x003f);
/* addiu[32] t0, $0, 0x3f */
/* 0x60 corresponds to GT_PCI0M0HD */
stw_p(p++, 0x8422); stw_p(p++, 0x9060);
/* sw t0, 0x60(t1) */
stw_p(p++, 0x0020); stw_p(p++, 0x00c1);
/* addiu[32] t0, $0, 0xc1 */
/* 0x80 corresponds to GT_PCI0M1LD */
stw_p(p++, 0x8422); stw_p(p++, 0x9080);
/* sw t0, 0x80(t1) */
stw_p(p++, 0x0020); stw_p(p++, 0x005e);
/* addiu[32] t0, $0, 0x5e */
#endif
/* 0x88 corresponds to GT_PCI0M1HD */
stw_p(p++, 0x8422); stw_p(p++, 0x9088);
/* sw t0, 0x88(t1) */
stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
stw_p(p++, NM_HI2(kernel_entry));
/* lui t9,%hi(kernel_entry) */
stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry));
/* ori t9,t9,%lo(kernel_entry) */
stw_p(p++, 0x4bf9); stw_p(p++, 0x0000);
/* jalrc t8 */
bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
}
/*
@ -839,6 +748,7 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
uint64_t kernel_entry)
{
uint32_t *p;
void *v;
/* Small bootloader */
p = (uint32_t *)base;
@ -875,54 +785,9 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
*
*/
/* Bus endianess is always reversed */
#if TARGET_BIG_ENDIAN
#define cpu_to_gt32 cpu_to_le32
#else
#define cpu_to_gt32 cpu_to_be32
#endif
/* move GT64120 registers from 0x14000000 to 0x1be00000 */
bl_gen_write_u32(&p, /* GT_ISD */
cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
cpu_to_gt32(0x1be00000 << 3));
/* setup MEM-to-PCI0 mapping */
/* setup PCI0 io window to 0x18000000-0x181fffff */
bl_gen_write_u32(&p, /* GT_PCI0IOLD */
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
cpu_to_gt32(0x18000000 << 3));
bl_gen_write_u32(&p, /* GT_PCI0IOHD */
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
cpu_to_gt32(0x08000000 << 3));
/* setup PCI0 mem windows */
bl_gen_write_u32(&p, /* GT_PCI0M0LD */
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
cpu_to_gt32(0x10000000 << 3));
bl_gen_write_u32(&p, /* GT_PCI0M0HD */
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
cpu_to_gt32(0x07e00000 << 3));
bl_gen_write_u32(&p, /* GT_PCI0M1LD */
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
cpu_to_gt32(0x18200000 << 3));
bl_gen_write_u32(&p, /* GT_PCI0M1HD */
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
cpu_to_gt32(0x0bc00000 << 3));
#undef cpu_to_gt32
bl_gen_jump_kernel(&p,
true, ENVP_VADDR - 64,
/*
* If semihosting is used, arguments have already been
* passed, so we preserve $a0.
*/
!semihosting_get_argc(), 2,
true, ENVP_VADDR,
true, ENVP_VADDR + 8,
true, loaderparams.ram_low_size,
kernel_entry);
v = p;
bl_setup_gt64120_jump_kernel(&v, run_addr, kernel_entry);
p = v;
/* YAMON subroutines */
p = (uint32_t *) (base + 0x800);
@ -966,7 +831,6 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
stl_p(p++, 0x00000000); /* nop */
stl_p(p++, 0x03e00009); /* jalr ra */
stl_p(p++, 0xa1040000); /* sb a0,0(t0) */
}
static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t *prom_buf, int index,
@ -1013,7 +877,6 @@ static uint64_t load_kernel(void)
uint32_t *prom_buf;
long prom_size;
int prom_index = 0;
uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr);
uint8_t rng_seed[32];
char rng_seed_hex[sizeof(rng_seed) * 2 + 1];
size_t rng_seed_prom_offset;
@ -1037,19 +900,10 @@ static uint64_t load_kernel(void)
}
/* Check where the kernel has been linked */
if (kernel_entry & 0x80000000ll) {
if (kvm_enabled()) {
error_report("KVM guest kernels must be linked in useg. "
"Did you forget to enable CONFIG_KVM_GUEST?");
exit(1);
}
xlate_to_kseg0 = cpu_mips_phys_to_kseg0;
} else {
/* if kernel entry is in useg it is probably a KVM T&E kernel */
mips_um_ksegs_enable();
xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0;
if (kernel_entry <= USEG_LIMIT) {
error_report("Trap-and-Emul kernels (Linux CONFIG_KVM_GUEST)"
" are not supported");
exit(1);
}
/* load initrd */
@ -1090,7 +944,7 @@ static uint64_t load_kernel(void)
if (initrd_size > 0) {
prom_set(prom_buf, prom_index++,
"rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
xlate_to_kseg0(NULL, initrd_offset),
cpu_mips_phys_to_kseg0(NULL, initrd_offset),
initrd_size, loaderparams.kernel_cmdline);
} else {
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
@ -1140,6 +994,31 @@ static void malta_mips_config(MIPSCPU *cpu)
}
}
static int malta_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
{
int slot;
slot = PCI_SLOT(pci_dev->devfn);
switch (slot) {
/* PIIX4 USB */
case 10:
return 3;
/* AMD 79C973 Ethernet */
case 11:
return 1;
/* Crystal 4281 Sound */
case 12:
return 2;
/* PCI slot 1 to 4 */
case 18 ... 21:
return ((slot - 18) + irq_num) & 0x03;
/* Unknown device, don't do any translation */
default:
return irq_num;
}
}
static void main_cpu_reset(void *opaque)
{
MIPSCPU *cpu = opaque;
@ -1157,11 +1036,6 @@ static void main_cpu_reset(void *opaque)
}
malta_mips_config(cpu);
if (kvm_enabled()) {
/* Start running from the bootloader we wrote to end of RAM */
env->active_tc.PC = 0x40000000 + loaderparams.ram_low_size;
}
}
static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
@ -1295,13 +1169,7 @@ void mips_malta_init(MachineState *machine)
fl_idx++;
if (kernel_filename) {
ram_low_size = MIN(ram_size, 256 * MiB);
/* For KVM we reserve 1MB of RAM for running bootloader */
if (kvm_enabled()) {
ram_low_size -= 0x100000;
bootloader_run_addr = cpu_mips_kvm_um_phys_to_kseg0(NULL, ram_low_size);
} else {
bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS);
}
bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS);
/* Write a small bootloader to the flash location. */
loaderparams.ram_size = ram_size;
@ -1318,20 +1186,8 @@ void mips_malta_init(MachineState *machine)
write_bootloader_nanomips(memory_region_get_ram_ptr(bios),
bootloader_run_addr, kernel_entry);
}
if (kvm_enabled()) {
/* Write the bootloader code @ the end of RAM, 1MB reserved */
write_bootloader(memory_region_get_ram_ptr(ram_low_preio) +
ram_low_size,
bootloader_run_addr, kernel_entry);
}
} else {
target_long bios_size = FLASH_SIZE;
/* The flash region isn't executable from a KVM guest */
if (kvm_enabled()) {
error_report("KVM enabled but no -kernel argument was specified. "
"Booting from flash is not supported with KVM.");
exit(1);
}
/* Load firmware from flash. */
if (!dinfo) {
/* Load a BIOS image. */
@ -1391,17 +1247,14 @@ void mips_malta_init(MachineState *machine)
stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
/* Northbridge */
dev = sysbus_create_simple("gt64120", -1, NULL);
dev = qdev_new("gt64120");
qdev_prop_set_bit(dev, "cpu-little-endian", !be);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
/*
* The whole address space decoded by the GT-64120A doesn't generate
* exception when accessing invalid memory. Create an empty slot to
* emulate this feature.
*/
empty_slot_init("GT64120", 0, 0x20000000);
pci_bus_map_irqs(pci_bus, malta_pci_slot_get_pirq);
/* Southbridge */
piix4 = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true,
piix4 = pci_create_simple_multifunction(pci_bus, PIIX4_PCI_DEVFN, true,
TYPE_PIIX4_PCI_DEVICE);
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0"));

2
hw/mips/meson.build
View File

@ -2,7 +2,7 @@ mips_ss = ss.source_set()
mips_ss.add(files('bootloader.c', 'mips_int.c'))
mips_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c'))
mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c'))
mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c'))
mips_ss.add(when: 'CONFIG_MALTA', if_true: files('malta.c'))
mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c'))
if 'CONFIG_TCG' in config_all

9
hw/mips/trace-events
View File

@ -1,6 +1,3 @@
# gt64xxx_pci.c
gt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64
gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64
gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64
gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64
gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64
# malta.c
malta_fpga_leds(const char *text) "LEDs %s"
malta_fpga_display(const char *text) "ASCII '%s'"

6
hw/pci-host/Kconfig
View File

@ -81,3 +81,9 @@ config MV64361
config DINO
bool
select PCI
config GT64120
bool
select PCI
select EMPTY_SLOT
select I8259

37
hw/pci-host/bonito.c
View File

@ -45,9 +45,9 @@
#include "hw/pci/pci_device.h"
#include "hw/irq.h"
#include "hw/mips/mips.h"
#include "hw/pci-host/bonito.h"
#include "hw/pci/pci_host.h"
#include "migration/vmstate.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
#include "hw/misc/unimp.h"
#include "hw/registerfields.h"
@ -239,9 +239,6 @@ struct BonitoState {
MemoryRegion pci_mem;
};
#define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost"
OBJECT_DECLARE_SIMPLE_TYPE(BonitoState, BONITO_PCI_HOST_BRIDGE)
#define TYPE_PCI_BONITO "Bonito"
OBJECT_DECLARE_SIMPLE_TYPE(PCIBonitoState, PCI_BONITO)
@ -593,9 +590,9 @@ static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num)
}
}
static void bonito_reset(void *opaque)
static void bonito_reset_hold(Object *obj)
{
PCIBonitoState *s = opaque;
PCIBonitoState *s = PCI_BONITO(obj);
uint32_t val = 0;
/* set the default value of north bridge registers */
@ -628,7 +625,7 @@ static const VMStateDescription vmstate_bonito = {
}
};
static void bonito_pcihost_realize(DeviceState *dev, Error **errp)
static void bonito_host_realize(DeviceState *dev, Error **errp)
{
PCIHostState *phb = PCI_HOST_BRIDGE(dev);
BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev);
@ -654,7 +651,7 @@ static void bonito_pcihost_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("pci.io", BONITO_PCIIO_BASE, 1 * MiB);
}
static void bonito_realize(PCIDevice *dev, Error **errp)
static void bonito_pci_realize(PCIDevice *dev, Error **errp)
{
PCIBonitoState *s = PCI_BONITO(dev);
SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost);
@ -739,8 +736,6 @@ static void bonito_realize(PCIDevice *dev, Error **errp)
pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c);
pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
qemu_register_reset(bonito_reset, s);
}
PCIBus *bonito_init(qemu_irq *pic)
@ -766,12 +761,14 @@ PCIBus *bonito_init(qemu_irq *pic)
return phb->bus;
}
static void bonito_class_init(ObjectClass *klass, void *data)
static void bonito_pci_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
k->realize = bonito_realize;
rc->phases.hold = bonito_reset_hold;
k->realize = bonito_pci_realize;
k->vendor_id = 0xdf53;
k->device_id = 0x00d5;
k->revision = 0x01;
@ -785,35 +782,35 @@ static void bonito_class_init(ObjectClass *klass, void *data)
dc->user_creatable = false;
}
static const TypeInfo bonito_info = {
static const TypeInfo bonito_pci_info = {
.name = TYPE_PCI_BONITO,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIBonitoState),
.class_init = bonito_class_init,
.class_init = bonito_pci_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ },
},
};
static void bonito_pcihost_class_init(ObjectClass *klass, void *data)
static void bonito_host_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = bonito_pcihost_realize;
dc->realize = bonito_host_realize;
}
static const TypeInfo bonito_pcihost_info = {
static const TypeInfo bonito_host_info = {
.name = TYPE_BONITO_PCI_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
.instance_size = sizeof(BonitoState),
.class_init = bonito_pcihost_class_init,
.class_init = bonito_host_class_init,
};
static void bonito_register_types(void)
{
type_register_static(&bonito_pcihost_info);
type_register_static(&bonito_info);
type_register_static(&bonito_host_info);
type_register_static(&bonito_pci_info);
}
type_init(bonito_register_types)

130
hw/mips/gt64xxx_pci.c → hw/pci-host/gt64120.c
View File

@ -26,8 +26,11 @@
#include "qapi/error.h"
#include "qemu/units.h"
#include "qemu/log.h"
#include "hw/qdev-properties.h"
#include "hw/registerfields.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_host.h"
#include "hw/misc/empty_slot.h"
#include "migration/vmstate.h"
#include "hw/intc/i8259.h"
#include "hw/irq.h"
@ -40,6 +43,9 @@
#define GT_CPU (0x000 >> 2)
#define GT_MULTI (0x120 >> 2)
REG32(GT_CPU, 0x000)
FIELD(GT_CPU, Endianness, 12, 1)
/* CPU Address Decode */
#define GT_SCS10LD (0x008 >> 2)
#define GT_SCS10HD (0x010 >> 2)
@ -209,6 +215,17 @@
#define GT_PCI0_CFGADDR (0xcf8 >> 2)
#define GT_PCI0_CFGDATA (0xcfc >> 2)
REG32(GT_PCI0_CMD, 0xc00)
FIELD(GT_PCI0_CMD, MByteSwap, 0, 1)
FIELD(GT_PCI0_CMD, SByteSwap, 16, 1)
#define R_GT_PCI0_CMD_ByteSwap_MASK \
(R_GT_PCI0_CMD_MByteSwap_MASK | R_GT_PCI0_CMD_SByteSwap_MASK)
REG32(GT_PCI1_CMD, 0xc80)
FIELD(GT_PCI1_CMD, MByteSwap, 0, 1)
FIELD(GT_PCI1_CMD, SByteSwap, 16, 1)
#define R_GT_PCI1_CMD_ByteSwap_MASK \
(R_GT_PCI1_CMD_MByteSwap_MASK | R_GT_PCI1_CMD_SByteSwap_MASK)
/* Interrupts */
#define GT_INTRCAUSE (0xc18 >> 2)
#define GT_INTRMASK (0xc1c >> 2)
@ -240,6 +257,9 @@ struct GT64120State {
PCI_MAPPING_ENTRY(ISD);
MemoryRegion pci0_mem;
AddressSpace pci0_mem_as;
/* properties */
bool cpu_little_endian;
};
/* Adjust range to avoid touching space which isn't mappable via PCI */
@ -282,6 +302,8 @@ static void gt64120_isd_mapping(GT64120State *s)
hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull;
hwaddr length = 0x1000;
memory_region_transaction_begin();
if (s->ISD_length) {
memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
}
@ -292,10 +314,58 @@ static void gt64120_isd_mapping(GT64120State *s)
s->ISD_start = start;
s->ISD_length = length;
memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
memory_region_transaction_commit();
}
static void gt64120_update_pci_cfgdata_mapping(GT64120State *s)
{
/* Indexed on MByteSwap bit, see Table 158: PCI_0 Command, Offset: 0xc00 */
static const MemoryRegionOps *pci_host_conf_ops[] = {
&pci_host_conf_be_ops, &pci_host_conf_le_ops
};
static const MemoryRegionOps *pci_host_data_ops[] = {
&pci_host_data_be_ops, &pci_host_data_le_ops
};
PCIHostState *phb = PCI_HOST_BRIDGE(s);
memory_region_transaction_begin();
/*
* The setting of the MByteSwap bit and MWordSwap bit in the PCI Internal
* Command Register determines how data transactions from the CPU to/from
* PCI are handled along with the setting of the Endianess bit in the CPU
* Configuration Register. See:
* - Table 16: 32-bit PCI Transaction Endianess
* - Table 158: PCI_0 Command, Offset: 0xc00
*/
if (memory_region_is_mapped(&phb->conf_mem)) {
memory_region_del_subregion(&s->ISD_mem, &phb->conf_mem);
object_unparent(OBJECT(&phb->conf_mem));
}
memory_region_init_io(&phb->conf_mem, OBJECT(phb),
pci_host_conf_ops[s->regs[GT_PCI0_CMD] & 1],
s, "pci-conf-idx", 4);
memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGADDR << 2,
&phb->conf_mem, 1);
if (memory_region_is_mapped(&phb->data_mem)) {
memory_region_del_subregion(&s->ISD_mem, &phb->data_mem);
object_unparent(OBJECT(&phb->data_mem));
}
memory_region_init_io(&phb->data_mem, OBJECT(phb),
pci_host_data_ops[s->regs[GT_PCI0_CMD] & 1],
s, "pci-conf-data", 4);
memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGDATA << 2,
&phb->data_mem, 1);
memory_region_transaction_commit();
}
static void gt64120_pci_mapping(GT64120State *s)
{
memory_region_transaction_begin();
/* Update PCI0IO mapping */
if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) {
/* Unmap old IO address */
@ -354,6 +424,8 @@ static void gt64120_pci_mapping(GT64120State *s)
&s->PCI0M1_mem);
}
}
memory_region_transaction_commit();
}
static int gt64120_post_load(void *opaque, int version_id)
@ -381,7 +453,6 @@ static void gt64120_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
GT64120State *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
uint32_t saddr = addr >> 2;
trace_gt64120_write(addr, val);
@ -584,6 +655,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
case GT_PCI0_CMD:
case GT_PCI1_CMD:
s->regs[saddr] = val & 0x0401fc0f;
gt64120_update_pci_cfgdata_mapping(s);
break;
case GT_PCI0_TOR:
case GT_PCI0_BS_SCS10:
@ -624,15 +696,9 @@ static void gt64120_writel(void *opaque, hwaddr addr,
saddr << 2, size, size << 1, val);
break;
case GT_PCI0_CFGADDR:
phb->config_reg = val & 0x80fffffc;
break;
case GT_PCI0_CFGDATA:
if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
val = bswap32(val);
}
if (phb->config_reg & (1u << 31)) {
pci_data_write(phb->bus, phb->config_reg, val, 4);
}
/* Mapped via in gt64120_pci_mapping() */
g_assert_not_reached();
break;
/* Interrupts */
@ -690,7 +756,6 @@ static uint64_t gt64120_readl(void *opaque,
hwaddr addr, unsigned size)
{
GT64120State *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
uint32_t val;
uint32_t saddr = addr >> 2;
@ -875,17 +940,9 @@ static uint64_t gt64120_readl(void *opaque,
/* PCI Internal */
case GT_PCI0_CFGADDR:
val = phb->config_reg;
break;
case GT_PCI0_CFGDATA:
if (!(phb->config_reg & (1 << 31))) {
val = 0xffffffff;
} else {
val = pci_data_read(phb->bus, phb->config_reg, 4);
}
if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
val = bswap32(val);
}
/* Mapped via in gt64120_pci_mapping() */
g_assert_not_reached();
break;
case GT_PCI0_CMD:
@ -986,11 +1043,7 @@ static void gt64120_reset(DeviceState *dev)
/* FIXME: Malta specific hw assumptions ahead */
/* CPU Configuration */
#if TARGET_BIG_ENDIAN
s->regs[GT_CPU] = 0x00000000;
#else
s->regs[GT_CPU] = 0x00001000;
#endif
s->regs[GT_CPU] = s->cpu_little_endian ? R_GT_CPU_Endianness_MASK : 0;
s->regs[GT_MULTI] = 0x00000003;
/* CPU Address decode */
@ -1097,11 +1150,7 @@ static void gt64120_reset(DeviceState *dev)
s->regs[GT_TC_CONTROL] = 0x00000000;
/* PCI Internal */
#if TARGET_BIG_ENDIAN
s->regs[GT_PCI0_CMD] = 0x00000000;
#else
s->regs[GT_PCI0_CMD] = 0x00010001;
#endif
s->regs[GT_PCI0_CMD] = s->cpu_little_endian ? R_GT_PCI0_CMD_ByteSwap_MASK : 0;
s->regs[GT_PCI0_TOR] = 0x0000070f;
s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
@ -1118,11 +1167,7 @@ static void gt64120_reset(DeviceState *dev)
s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
#if TARGET_BIG_ENDIAN
s->regs[GT_PCI1_CMD] = 0x00000000;
#else
s->regs[GT_PCI1_CMD] = 0x00010001;
#endif
s->regs[GT_PCI1_CMD] = s->cpu_little_endian ? R_GT_PCI1_CMD_ByteSwap_MASK : 0;
s->regs[GT_PCI1_TOR] = 0x0000070f;
s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
@ -1145,6 +1190,7 @@ static void gt64120_reset(DeviceState *dev)
gt64120_isd_mapping(s);
gt64120_pci_mapping(s);
gt64120_update_pci_cfgdata_mapping(s);
}
static void gt64120_realize(DeviceState *dev, Error **errp)
@ -1162,6 +1208,13 @@ static void gt64120_realize(DeviceState *dev, Error **errp)
PCI_DEVFN(18, 0), TYPE_PCI_BUS);
pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
/*
* The whole address space decoded by the GT-64120A doesn't generate
* exception when accessing invalid memory. Create an empty slot to
* emulate this feature.
*/
empty_slot_init("GT64120", 0, 0x20000000);
}
static void gt64120_pci_realize(PCIDevice *d, Error **errp)
@ -1208,11 +1261,18 @@ static const TypeInfo gt64120_pci_info = {
},
};
static Property gt64120_properties[] = {
DEFINE_PROP_BOOL("cpu-little-endian", GT64120State,
cpu_little_endian, false),
DEFINE_PROP_END_OF_LIST(),
};
static void gt64120_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
device_class_set_props(dc, gt64120_properties);
dc->realize = gt64120_realize;
dc->reset = gt64120_reset;
dc->vmsd = &vmstate_gt64120;

1
hw/pci-host/meson.build
View File

@ -1,6 +1,7 @@
pci_ss = ss.source_set()
pci_ss.add(when: 'CONFIG_PAM', if_true: files('pam.c'))
pci_ss.add(when: 'CONFIG_PCI_BONITO', if_true: files('bonito.c'))
pci_ss.add(when: 'CONFIG_GT64120', if_true: files('gt64120.c'))
pci_ss.add(when: 'CONFIG_PCI_EXPRESS_DESIGNWARE', if_true: files('designware.c'))
pci_ss.add(when: 'CONFIG_PCI_EXPRESS_GENERIC_BRIDGE', if_true: files('gpex.c'))
pci_ss.add(when: ['CONFIG_PCI_EXPRESS_GENERIC_BRIDGE', 'CONFIG_ACPI'], if_true: files('gpex-acpi.c'))

3
hw/pci-host/raven.c
View File

@ -258,7 +258,8 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
qdev_init_gpio_in(d, raven_change_gpio, 1);
pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS);
pci_bus_irqs(&s->pci_bus, raven_set_irq, s, PCI_NUM_PINS);
pci_bus_map_irqs(&s->pci_bus, raven_map_irq);
memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
"pci-conf-idx", 4);

7
hw/pci-host/trace-events
View File

@ -6,6 +6,13 @@ bonito_spciconf_small_access(uint64_t addr, unsigned size) "PCI config address i
# grackle.c
grackle_set_irq(int irq_num, int level) "set_irq num %d level %d"
# gt64120.c
gt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64
gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64
gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64
gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64
gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64
# mv64361.c
mv64361_region_map(const char *name, uint64_t poffs, uint64_t size, uint64_t moffs) "Mapping %s 0x%"PRIx64"+0x%"PRIx64" @ 0x%"PRIx64
mv64361_region_enable(const char *op, int num) "Should %s region %d"

3
hw/pci-host/versatile.c
View File

@ -422,7 +422,8 @@ static void pci_vpb_realize(DeviceState *dev, Error **errp)
mapfn = pci_vpb_map_irq;
}
pci_bus_irqs(&s->pci_bus, pci_vpb_set_irq, mapfn, s->irq, 4);
pci_bus_irqs(&s->pci_bus, pci_vpb_set_irq, s->irq, 4);
pci_bus_map_irqs(&s->pci_bus, mapfn);
/* Our memory regions are:
* 0 : our control registers

12
hw/pci/pci.c
View File

@ -280,6 +280,7 @@ static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
PCIBus *bus;
for (;;) {
bus = pci_get_bus(pci_dev);
assert(bus->map_irq);
irq_num = bus->map_irq(pci_dev, irq_num);
if (bus->set_irq)
break;
@ -518,16 +519,20 @@ void pci_root_bus_cleanup(PCIBus *bus)
qbus_unrealize(BUS(bus));
}
void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq,
void *irq_opaque, int nirq)
{
bus->set_irq = set_irq;
bus->map_irq = map_irq;
bus->irq_opaque = irq_opaque;
bus->nirq = nirq;
bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
}
void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq)
{
bus->map_irq = map_irq;
}
void pci_bus_irqs_cleanup(PCIBus *bus)
{
bus->set_irq = NULL;
@ -549,7 +554,8 @@ PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
bus = pci_root_bus_new(parent, name, address_space_mem,
address_space_io, devfn_min, typename);
pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
pci_bus_irqs(bus, set_irq, irq_opaque, nirq);
pci_bus_map_irqs(bus, map_irq);
return bus;
}

6
hw/pci/pci_host.c
View File

@ -118,6 +118,9 @@ void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, unsigned len)
uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
if (!pci_dev) {
trace_pci_cfg_write("empty", extract32(addr, 16, 8),
extract32(addr, 11, 5), extract32(addr, 8, 3),
config_addr, val);
return;
}
@ -131,6 +134,9 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, unsigned len)
uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
if (!pci_dev) {
trace_pci_cfg_read("empty", extract32(addr, 16, 8),
extract32(addr, 11, 5), extract32(addr, 8, 3),
config_addr, ~0x0);
return ~0x0;
}

3
hw/remote/machine.c
View File

@ -63,8 +63,9 @@ static void remote_machine_init(MachineState *machine)
} else {
remote_iohub_init(&s->iohub);
pci_bus_irqs(pci_host->bus, remote_iohub_set_irq, remote_iohub_map_irq,
pci_bus_irqs(pci_host->bus, remote_iohub_set_irq,
&s->iohub, REMOTE_IOHUB_NB_PIRQS);
pci_bus_map_irqs(pci_host->bus, remote_iohub_map_irq);
}
qbus_set_hotplug_handler(BUS(pci_host->bus), OBJECT(s));

4
hw/remote/vfio-user-obj.c
View File

@ -665,8 +665,8 @@ void vfu_object_set_bus_irq(PCIBus *pci_bus)
int bus_num = pci_bus_num(pci_bus);
int max_bdf = PCI_BUILD_BDF(bus_num, PCI_DEVFN_MAX - 1);
pci_bus_irqs(pci_bus, vfu_object_set_irq, vfu_object_map_irq, pci_bus,
max_bdf);
pci_bus_irqs(pci_bus, vfu_object_set_irq, pci_bus, max_bdf);
pci_bus_map_irqs(pci_bus, vfu_object_map_irq);
}
static int vfu_object_device_reset(vfu_ctx_t *vfu_ctx, vfu_reset_type_t type)

20
hw/rtc/mc146818rtc.c
View File

@ -27,6 +27,7 @@
#include "qemu/module.h"
#include "qemu/bcd.h"
#include "hw/acpi/acpi_aml_interface.h"
#include "hw/intc/kvm_irqcount.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
@ -44,11 +45,6 @@
#include "qapi/visitor.h"
#include "hw/rtc/mc146818rtc_regs.h"
#ifdef TARGET_I386
#include "qapi/qapi-commands-misc-target.h"
#include "hw/i386/apic.h"
#endif
//#define DEBUG_CMOS
//#define DEBUG_COALESCED
@ -112,7 +108,6 @@ static void rtc_coalesced_timer_update(RTCState *s)
static QLIST_HEAD(, RTCState) rtc_devices =
QLIST_HEAD_INITIALIZER(rtc_devices);
#ifdef TARGET_I386
void qmp_rtc_reset_reinjection(Error **errp)
{
RTCState *s;
@ -124,9 +119,9 @@ void qmp_rtc_reset_reinjection(Error **errp)
static bool rtc_policy_slew_deliver_irq(RTCState *s)
{
apic_reset_irq_delivered();
kvm_reset_irq_delivered();
qemu_irq_raise(s->irq);
return apic_get_irq_delivered();
return kvm_get_irq_delivered();
}
static void rtc_coalesced_timer(void *opaque)
@ -145,13 +140,6 @@ static void rtc_coalesced_timer(void *opaque)
rtc_coalesced_timer_update(s);
}
#else
static bool rtc_policy_slew_deliver_irq(RTCState *s)
{
assert(0);
return false;
}
#endif
static uint32_t rtc_periodic_clock_ticks(RTCState *s)
{
@ -922,12 +910,10 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
rtc_set_date_from_host(isadev);
switch (s->lost_tick_policy) {
#ifdef TARGET_I386
case LOST_TICK_POLICY_SLEW:
s->coalesced_timer =
timer_new_ns(rtc_clock, rtc_coalesced_timer, s);
break;
#endif
case LOST_TICK_POLICY_DISCARD:
break;
default:

3
hw/rtc/meson.build
View File

@ -13,5 +13,4 @@ softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_rtc.c'))
softmmu_ss.add(when: 'CONFIG_GOLDFISH_RTC', if_true: files('goldfish_rtc.c'))
softmmu_ss.add(when: 'CONFIG_LS7A_RTC', if_true: files('ls7a_rtc.c'))
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-rtc.c'))
specific_ss.add(when: 'CONFIG_MC146818RTC', if_true: files('mc146818rtc.c'))
softmmu_ss.add(when: 'CONFIG_MC146818RTC', if_true: files('mc146818rtc.c'))

16
hw/usb/hcd-uhci.c
View File

@ -1292,56 +1292,56 @@ void uhci_data_class_init(ObjectClass *klass, void *data)
static UHCIInfo uhci_info[] = {
{
.name = "piix3-usb-uhci",
.name = TYPE_PIIX3_USB_UHCI,
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82371SB_2,
.revision = 0x01,
.irq_pin = 3,
.unplug = true,
},{
.name = "piix4-usb-uhci",
.name = TYPE_PIIX4_USB_UHCI,
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82371AB_2,
.revision = 0x01,
.irq_pin = 3,
.unplug = true,
},{
.name = "ich9-usb-uhci1", /* 00:1d.0 */
.name = TYPE_ICH9_USB_UHCI(1), /* 00:1d.0 */
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1,
.revision = 0x03,
.irq_pin = 0,
.unplug = false,
},{
.name = "ich9-usb-uhci2", /* 00:1d.1 */
.name = TYPE_ICH9_USB_UHCI(2), /* 00:1d.1 */
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2,
.revision = 0x03,
.irq_pin = 1,
.unplug = false,
},{
.name = "ich9-usb-uhci3", /* 00:1d.2 */
.name = TYPE_ICH9_USB_UHCI(3), /* 00:1d.2 */
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3,
.revision = 0x03,
.irq_pin = 2,
.unplug = false,
},{
.name = "ich9-usb-uhci4", /* 00:1a.0 */
.name = TYPE_ICH9_USB_UHCI(4), /* 00:1a.0 */
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4,
.revision = 0x03,
.irq_pin = 0,
.unplug = false,
},{
.name = "ich9-usb-uhci5", /* 00:1a.1 */
.name = TYPE_ICH9_USB_UHCI(5), /* 00:1a.1 */
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5,
.revision = 0x03,
.irq_pin = 1,
.unplug = false,
},{
.name = "ich9-usb-uhci6", /* 00:1a.2 */
.name = TYPE_ICH9_USB_UHCI(6), /* 00:1a.2 */
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6,
.revision = 0x03,

4
hw/usb/hcd-uhci.h
View File

@ -91,4 +91,8 @@ typedef struct UHCIInfo {
void uhci_data_class_init(ObjectClass *klass, void *data);
void usb_uhci_common_realize(PCIDevice *dev, Error **errp);
#define TYPE_PIIX3_USB_UHCI "piix3-usb-uhci"
#define TYPE_PIIX4_USB_UHCI "piix4-usb-uhci"
#define TYPE_ICH9_USB_UHCI(fn) "ich9-usb-uhci" #fn
#endif

1
include/exec/poison.h
View File

@ -74,7 +74,6 @@
#pragma GCC poison CONFIG_M68K_DIS
#pragma GCC poison CONFIG_MICROBLAZE_DIS
#pragma GCC poison CONFIG_MIPS_DIS
#pragma GCC poison CONFIG_NANOMIPS_DIS
#pragma GCC poison CONFIG_NIOS2_DIS
#pragma GCC poison CONFIG_PPC_DIS
#pragma GCC poison CONFIG_RISCV_DIS

2
include/hw/i386/apic.h
View File

@ -9,8 +9,6 @@ int apic_accept_pic_intr(DeviceState *s);
void apic_deliver_pic_intr(DeviceState *s, int level);
void apic_deliver_nmi(DeviceState *d);
int apic_get_interrupt(DeviceState *s);
void apic_reset_irq_delivered(void);
int apic_get_irq_delivered(void);
void cpu_set_apic_base(DeviceState *s, uint64_t val);
uint64_t cpu_get_apic_base(DeviceState *s);
void cpu_set_apic_tpr(DeviceState *s, uint8_t val);

1
include/hw/i386/apic_internal.h
View File

@ -199,7 +199,6 @@ typedef struct VAPICState {
extern bool apic_report_tpr_access;
void apic_report_irq_delivered(int delivered);
bool apic_next_timer(APICCommonState *s, int64_t current_time);
void apic_enable_tpr_access_reporting(DeviceState *d, bool enable);
void apic_enable_vapic(DeviceState *d, hwaddr paddr);

6
include/hw/intc/i8259.h
View File

@ -3,10 +3,10 @@
/* i8259.c */
extern DeviceState *isa_pic;
extern PICCommonState *isa_pic;
qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
qemu_irq *kvm_i8259_init(ISABus *bus);
int pic_get_output(DeviceState *d);
int pic_read_irq(DeviceState *d);
int pic_get_output(PICCommonState *s);
int pic_read_irq(PICCommonState *s);
#endif

10
include/hw/intc/kvm_irqcount.h Normal file
View File

@ -0,0 +1,10 @@
/* SPDX-License-Identifier: LGPL-2.1-or-later */
#ifndef KVM_IRQCOUNT_H
#define KVM_IRQCOUNT_H
void kvm_report_irq_delivered(int delivered);
void kvm_reset_irq_delivered(void);
int kvm_get_irq_delivered(void);
#endif

10
include/hw/mips/bootloader.h
View File

@ -11,16 +11,16 @@
#include "exec/cpu-defs.h"
void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr);
void bl_gen_jump_kernel(uint32_t **p,
void bl_gen_jump_to(void **ptr, target_ulong jump_addr);
void bl_gen_jump_kernel(void **ptr,
bool set_sp, target_ulong sp,
bool set_a0, target_ulong a0,
bool set_a1, target_ulong a1,
bool set_a2, target_ulong a2,
bool set_a3, target_ulong a3,
target_ulong kernel_addr);
void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val);
void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val);
void bl_gen_write_u64(uint32_t **p, target_ulong addr, uint64_t val);
void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val);
void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val);
void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val);
#endif

18
include/hw/pci-host/bonito.h Normal file
View File

@ -0,0 +1,18 @@
/*
* QEMU Bonito64 north bridge support
*
* Copyright (c) 2008 yajin (yajin@vm-kernel.org)
* Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_PCI_HOST_BONITO_H
#define HW_PCI_HOST_BONITO_H
#include "qom/object.h"
#define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost"
OBJECT_DECLARE_SIMPLE_TYPE(BonitoState, BONITO_PCI_HOST_BRIDGE)
#endif

3
include/hw/pci/pci.h
View File

@ -282,8 +282,9 @@ PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
MemoryRegion *address_space_io,
uint8_t devfn_min, const char *typename);
void pci_root_bus_cleanup(PCIBus *bus);
void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq,
void *irq_opaque, int nirq);
void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq);
void pci_bus_irqs_cleanup(PCIBus *bus);
int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
/* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */

1
include/hw/rtc/mc146818rtc.h
View File

@ -55,5 +55,6 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
qemu_irq intercept_irq);
void rtc_set_memory(ISADevice *dev, int addr, int val);
int rtc_get_memory(ISADevice *dev, int addr);
void qmp_rtc_reset_reinjection(Error **errp);
#endif /* HW_RTC_MC146818RTC_H */

1
include/qemu/typedefs.h
View File

@ -99,6 +99,7 @@ typedef struct PCIExpressDevice PCIExpressDevice;
typedef struct PCIExpressHost PCIExpressHost;
typedef struct PCIHostDeviceAddress PCIHostDeviceAddress;
typedef struct PCIHostState PCIHostState;
typedef struct PICCommonState PICCommonState;
typedef struct PostcopyDiscardState PostcopyDiscardState;
typedef struct Property Property;
typedef struct PropertyInfo PropertyInfo;

5
meson.build
View File

@ -2490,11 +2490,6 @@ disassemblers = {
'xtensa' : ['CONFIG_XTENSA_DIS'],
'loongarch' : ['CONFIG_LOONGARCH_DIS'],
}
if link_language == 'cpp'
disassemblers += {
'mips' : [ 'CONFIG_MIPS_DIS', 'CONFIG_NANOMIPS_DIS'],
}
endif
have_ivshmem = config_host_data.get('CONFIG_EVENTFD')
host_kconfig = \

2
scripts/git.orderfile
View File

@ -9,6 +9,8 @@
# git config diff.orderFile scripts/git.orderfile
#
MAINTAINERS
# Documentation
docs/*
*.rst

6
softmmu/rtc.c
View File

@ -33,6 +33,7 @@
#include "sysemu/replay.h"
#include "sysemu/sysemu.h"
#include "sysemu/rtc.h"
#include "hw/rtc/mc146818rtc.h"
static enum {
RTC_BASE_UTC,
@ -177,10 +178,13 @@ void configure_rtc(QemuOpts *opts)
value = qemu_opt_get(opts, "driftfix");
if (value) {
if (!strcmp(value, "slew")) {
object_register_sugar_prop("mc146818rtc",
object_register_sugar_prop(TYPE_MC146818_RTC,
"lost_tick_policy",
"slew",
false);
if (!object_class_by_name(TYPE_MC146818_RTC)) {
warn_report("driftfix 'slew' is not available with this machine");
}
} else if (!strcmp(value, "none")) {
/* discard is default */
} else {

38
target/mips/cpu.c
View File

@ -32,7 +32,6 @@
#include "hw/qdev-properties.h"
#include "hw/qdev-clock.h"
#include "semihosting/semihost.h"
#include "qapi/qapi-commands-machine-target.h"
#include "fpu_helper.h"
const char regnames[32][3] = {
@ -292,12 +291,7 @@ static void mips_cpu_reset_hold(Object *obj)
env->tlb->tlb_in_use = env->tlb->nb_tlb;
env->CP0_Wired = 0;
env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId;
env->CP0_EBase = (cs->cpu_index & 0x3FF);
if (mips_um_ksegs_enabled()) {
env->CP0_EBase |= 0x40000000;
} else {
env->CP0_EBase |= (int32_t)0x80000000;
}
env->CP0_EBase = KSEG0_BASE | (cs->cpu_index & 0x3FF);
if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
}
@ -439,9 +433,7 @@ static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
info->print_insn = print_insn_little_mips;
#endif
} else {
#if defined(CONFIG_NANOMIPS_DIS)
info->print_insn = print_insn_nanomips;
#endif
}
}
@ -631,34 +623,6 @@ static void mips_cpu_register_types(void)
type_init(mips_cpu_register_types)
static void mips_cpu_add_definition(gpointer data, gpointer user_data)
{
ObjectClass *oc = data;
CpuDefinitionInfoList **cpu_list = user_data;
CpuDefinitionInfo *info;
const char *typename;
typename = object_class_get_name(oc);
info = g_malloc0(sizeof(*info));
info->name = g_strndup(typename,
strlen(typename) - strlen("-" TYPE_MIPS_CPU));
info->q_typename = g_strdup(typename);
QAPI_LIST_PREPEND(*cpu_list, info);
}
CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
{
CpuDefinitionInfoList *cpu_list = NULL;
GSList *list;
list = object_class_get_list(TYPE_MIPS_CPU, false);
g_slist_foreach(list, mips_cpu_add_definition, &cpu_list);
g_slist_free(list);
return cpu_list;
}
/* Could be used by generic CPU object */
MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
{

3
target/mips/cpu.h
View File

@ -1296,11 +1296,8 @@ void cpu_set_exception_base(int vp_index, target_ulong address);
uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr);
uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr);
bool mips_um_ksegs_enabled(void);
void mips_um_ksegs_enable(void);
#if !defined(CONFIG_USER_ONLY)

3
target/mips/internal.h
View File

@ -99,9 +99,6 @@ int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL)
#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL)
#if !defined(CONFIG_USER_ONLY)
enum {

11
target/mips/kvm.c
View File

@ -1268,25 +1268,16 @@ int kvm_arch_msi_data_to_gsi(uint32_t data)
int mips_kvm_type(MachineState *machine, const char *vm_type)
{
#if defined(KVM_CAP_MIPS_VZ) || defined(KVM_CAP_MIPS_TE)
#if defined(KVM_CAP_MIPS_VZ)
int r;
KVMState *s = KVM_STATE(machine->accelerator);
#endif
#if defined(KVM_CAP_MIPS_VZ)
r = kvm_check_extension(s, KVM_CAP_MIPS_VZ);
if (r > 0) {
return KVM_VM_MIPS_VZ;
}
#endif
#if defined(KVM_CAP_MIPS_TE)
r = kvm_check_extension(s, KVM_CAP_MIPS_TE);
if (r > 0) {
return KVM_VM_MIPS_TE;
}
#endif
return -1;
}

17
target/mips/sysemu/addr.c
View File

@ -23,8 +23,6 @@
#include "qemu/osdep.h"
#include "cpu.h"
static int mips_um_ksegs;
uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr)
{
return addr & 0x1fffffffll;
@ -35,11 +33,6 @@ uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr)
return addr | ~0x7fffffffll;
}
uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr)
{
return addr | 0x40000000ll;
}
uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr)
{
return addr & 0x1fffffffll;
@ -49,13 +42,3 @@ uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr)
{
return (addr & 0x1fffffffll) | 0xffffffffa0000000ll;
}
bool mips_um_ksegs_enabled(void)
{
return mips_um_ksegs;
}
void mips_um_ksegs_enable(void)
{
mips_um_ksegs = 1;
}

1
target/mips/sysemu/meson.build
View File

@ -3,5 +3,6 @@ mips_softmmu_ss.add(files(
'cp0.c',
'cp0_timer.c',
'machine.c',
'mips-qmp-cmds.c',
'physaddr.c',
))

39
target/mips/sysemu/mips-qmp-cmds.c Normal file
View File

@ -0,0 +1,39 @@
/*
* QEMU MIPS CPU (monitor definitions)
*
* SPDX-FileCopyrightText: 2012 SUSE LINUX Products GmbH
*
* SPDX-License-Identifier: LGPL-2.1-or-later
*/
#include "qemu/osdep.h"
#include "qapi/qapi-commands-machine-target.h"
#include "cpu.h"
static void mips_cpu_add_definition(gpointer data, gpointer user_data)
{
ObjectClass *oc = data;
CpuDefinitionInfoList **cpu_list = user_data;
CpuDefinitionInfo *info;
const char *typename;
typename = object_class_get_name(oc);
info = g_malloc0(sizeof(*info));
info->name = g_strndup(typename,
strlen(typename) - strlen("-" TYPE_MIPS_CPU));
info->q_typename = g_strdup(typename);
QAPI_LIST_PREPEND(*cpu_list, info);
}
CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
{
CpuDefinitionInfoList *cpu_list = NULL;
GSList *list;
list = object_class_get_list(TYPE_MIPS_CPU, false);
g_slist_foreach(list, mips_cpu_add_definition, &cpu_list);
g_slist_free(list);
return cpu_list;
}

13
target/mips/sysemu/physaddr.c
View File

@ -130,19 +130,6 @@ int get_physical_address(CPUMIPSState *env, hwaddr *physical,
/* effective address (modified for KVM T&E kernel segments) */
target_ulong address = real_address;
if (mips_um_ksegs_enabled()) {
/* KVM T&E adds guest kernel segments in useg */
if (real_address >= KVM_KSEG0_BASE) {
if (real_address < KVM_KSEG2_BASE) {
/* kseg0 */
address += KSEG0_BASE - KVM_KSEG0_BASE;
} else if (real_address <= USEG_LIMIT) {
/* kseg2/3 */
address += KSEG2_BASE - KVM_KSEG2_BASE;
}
}
}
if (address <= USEG_LIMIT) {
/* useg */
uint16_t segctl;

47
tests/avocado/machine_mips_malta.py
View File

@ -11,11 +11,13 @@ import os
import gzip
import logging
from avocado import skipUnless
from avocado_qemu import QemuSystemTest
from avocado_qemu import wait_for_console_pattern
from avocado.utils import archive
from avocado import skipIf
from avocado import skipUnless
from avocado.utils import archive
from avocado_qemu import QemuSystemTest
from avocado_qemu import exec_command_and_wait_for_pattern
from avocado_qemu import interrupt_interactive_console_until_pattern
from avocado_qemu import wait_for_console_pattern
NUMPY_AVAILABLE = True
@ -118,3 +120,40 @@ class MaltaMachineFramebuffer(QemuSystemTest):
:avocado: tags=mips:smp
"""
self.do_test_i6400_framebuffer_logo(8)
class MaltaMachine(QemuSystemTest):
def do_test_yamon(self):
rom_url = ('http://www.imgtec.com/tools/mips-tools/downloads/'
'yamon/yamon-bin-02.22.zip')
rom_hash = '8da7ecddbc5312704b8b324341ee238189bde480'
zip_path = self.fetch_asset(rom_url, asset_hash=rom_hash)
archive.extract(zip_path, self.workdir)
yamon_path = os.path.join(self.workdir, 'yamon-02.22.bin')
self.vm.set_console()
self.vm.add_args('-bios', yamon_path)
self.vm.launch()
prompt = 'YAMON>'
pattern = 'YAMON ROM Monitor'
interrupt_interactive_console_until_pattern(self, pattern, prompt)
wait_for_console_pattern(self, prompt)
self.vm.shutdown()
def test_mipsel_malta_yamon(self):
"""
:avocado: tags=arch:mipsel
:avocado: tags=machine:malta
:avocado: tags=endian:little
"""
self.do_test_yamon()
def test_mips64el_malta_yamon(self):
"""
:avocado: tags=arch:mips64el
:avocado: tags=machine:malta
:avocado: tags=endian:little
"""
self.do_test_yamon()