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target/riscv/tcg: add riscv_cpu_write_misa_bit()

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We have two instances of the setting/clearing a MISA bit from
env->misa_ext and env->misa_ext_mask pattern. And the next patch will
end up adding one more.

Create a helper to avoid code repetition.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231218125334.37184-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-12-18 09:53:20 -03:00 committed by Alistair Francis
parent 21915d16c6
commit a8c31f935c
1 changed files with 18 additions and 14 deletions
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32
target/riscv/tcg/tcg-cpu.c
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@ -42,6 +42,20 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
GUINT_TO_POINTER(ext_offset));
}
static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit,
bool enabled)
{
CPURISCVState *env = &cpu->env;
if (enabled) {
env->misa_ext |= bit;
env->misa_ext_mask |= bit;
} else {
env->misa_ext &= ~bit;
env->misa_ext_mask &= ~bit;
}
}
static void riscv_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
@ -833,13 +847,9 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
*/
env->priv_ver = PRIV_VERSION_1_12_0;
}
env->misa_ext |= misa_bit;
env->misa_ext_mask |= misa_bit;
} else {
env->misa_ext &= ~misa_bit;
env->misa_ext_mask &= ~misa_bit;
}
riscv_cpu_write_misa_bit(cpu, misa_bit, value);
}
static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
@ -883,7 +893,6 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
*/
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
{
CPURISCVState *env = &RISCV_CPU(cpu_obj)->env;
bool use_def_vals = riscv_cpu_is_generic(cpu_obj);
int i;
@ -904,13 +913,8 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
NULL, (void *)misa_cfg);
object_property_set_description(cpu_obj, name, desc);
if (use_def_vals) {
if (misa_cfg->enabled) {
env->misa_ext |= bit;
env->misa_ext_mask |= bit;
} else {
env->misa_ext &= ~bit;
env->misa_ext_mask &= ~bit;
}
riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit,
misa_cfg->enabled);
}
}
}