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tcg-sparc: Tidy tcg_out_tlb_load interface

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Pass address registers explicitly, rather than as indicies of args[].
It's two argument registers either way.  Use more TCGReg as appropriate.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2013-09-06 15:01:14 -07:00
parent eef0d9e740
commit a8b12c108c
1 changed files with 30 additions and 40 deletions
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70
tcg/sparc/tcg-target.c
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@ -863,8 +863,7 @@ static const void * const qemu_st_helpers[4] = {
/* Perform the TLB load and compare. /* Perform the TLB load and compare.
Inputs: Inputs:
ADDRLO_IDX contains the index into ARGS of the low part of the ADDRLO and ADDRHI contain the possible two parts of the address.
address; the high part of the address is at ADDR_LOW_IDX+1.
MEM_INDEX and S_BITS are the memory context and log2 size of the load. MEM_INDEX and S_BITS are the memory context and log2 size of the load.
@ -874,20 +873,19 @@ static const void * const qemu_st_helpers[4] = {
The result of the TLB comparison is in %[ix]cc. The sanitized address The result of the TLB comparison is in %[ix]cc. The sanitized address
is in the returned register, maybe %o0. The TLB addend is in %o1. */ is in the returned register, maybe %o0. The TLB addend is in %o1. */
static int tcg_out_tlb_load(TCGContext *s, int addrlo_idx, int mem_index, static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
TCGMemOp s_bits, const TCGArg *args, int which) int mem_index, TCGMemOp s_bits, int which)
{ {
const int addrlo = args[addrlo_idx]; const TCGReg r0 = TCG_REG_O0;
const int r0 = TCG_REG_O0; const TCGReg r1 = TCG_REG_O1;
const int r1 = TCG_REG_O1; const TCGReg r2 = TCG_REG_O2;
const int r2 = TCG_REG_O2; TCGReg addr = addrlo;
int addr = addrlo;
int tlb_ofs; int tlb_ofs;
if (TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 64) { if (TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 64) {
/* Assemble the 64-bit address in R0. */ /* Assemble the 64-bit address in R0. */
tcg_out_arithi(s, r0, addrlo, 0, SHIFT_SRL); tcg_out_arithi(s, r0, addrlo, 0, SHIFT_SRL);
tcg_out_arithi(s, r1, args[addrlo_idx + 1], 32, SHIFT_SLLX); tcg_out_arithi(s, r1, addrhi, 32, SHIFT_SLLX);
tcg_out_arith(s, r0, r0, r1, ARITH_OR); tcg_out_arith(s, r0, r0, r1, ARITH_OR);
addr = r0; addr = r0;
} }
@ -965,24 +963,23 @@ static const int qemu_st_opc[16] = {
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp memop) static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp memop)
{ {
int addrlo_idx = 1, datalo, datahi, addr_reg; TCGReg addrlo, datalo, datahi, addr_reg;
TCGMemOp s_bits = memop & MO_SIZE; TCGMemOp s_bits = memop & MO_SIZE;
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
int memi_idx, memi, n; TCGReg addrhi;
int memi, n;
uint32_t *label_ptr[2]; uint32_t *label_ptr[2];
#endif #endif
datahi = datalo = args[0]; datalo = *args++;
if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { datahi = (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64 ? *args++ : 0);
datahi = args[1]; addr_reg = addrlo = *args++;
addrlo_idx = 2;
}
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
memi_idx = addrlo_idx + 1 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS); addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
memi = args[memi_idx]; memi = *args++;
addr_reg = tcg_out_tlb_load(s, addrlo_idx, memi, s_bits, args, addr_reg = tcg_out_tlb_load(s, addrlo, addrhi, memi, s_bits,
offsetof(CPUTLBEntry, addr_read)); offsetof(CPUTLBEntry, addr_read));
if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
@ -1031,11 +1028,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp memop)
n = 0; n = 0;
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[n++], TCG_AREG0); tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[n++], TCG_AREG0);
if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], addrhi);
args[addrlo_idx + 1]);
} }
tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], addrlo);
args[addrlo_idx]);
/* qemu_ld_helper[s_bits](arg0, arg1) */ /* qemu_ld_helper[s_bits](arg0, arg1) */
tcg_out_calli(s, (uintptr_t)qemu_ld_helpers[s_bits]); tcg_out_calli(s, (uintptr_t)qemu_ld_helpers[s_bits]);
@ -1076,7 +1071,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp memop)
*label_ptr[1] |= INSN_OFF19((unsigned long)s->code_ptr - *label_ptr[1] |= INSN_OFF19((unsigned long)s->code_ptr -
(unsigned long)label_ptr[1]); (unsigned long)label_ptr[1]);
#else #else
addr_reg = args[addrlo_idx];
if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) { if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) {
tcg_out_arithi(s, TCG_REG_T1, addr_reg, 0, SHIFT_SRL); tcg_out_arithi(s, TCG_REG_T1, addr_reg, 0, SHIFT_SRL);
addr_reg = TCG_REG_T1; addr_reg = TCG_REG_T1;
@ -1102,24 +1096,23 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp memop)
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGMemOp memop) static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGMemOp memop)
{ {
int addrlo_idx = 1, datalo, datahi, addr_reg; TCGReg addrlo, datalo, datahi, addr_reg;
TCGMemOp s_bits = memop & MO_SIZE; TCGMemOp s_bits = memop & MO_SIZE;
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
int memi_idx, memi, n, datafull; TCGReg addrhi, datafull;
int memi, n;
uint32_t *label_ptr; uint32_t *label_ptr;
#endif #endif
datahi = datalo = args[0]; datalo = *args++;
if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { datahi = (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64 ? *args++ : 0);
datahi = args[1]; addr_reg = addrlo = *args++;
addrlo_idx = 2;
}
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
memi_idx = addrlo_idx + 1 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS); addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
memi = args[memi_idx]; memi = *args++;
addr_reg = tcg_out_tlb_load(s, addrlo_idx, memi, s_bits, args, addr_reg = tcg_out_tlb_load(s, addrlo, addrhi, memi, s_bits,
offsetof(CPUTLBEntry, addr_write)); offsetof(CPUTLBEntry, addr_write));
datafull = datalo; datafull = datalo;
@ -1145,11 +1138,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGMemOp memop)
n = 0; n = 0;
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[n++], TCG_AREG0); tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[n++], TCG_AREG0);
if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], addrhi);
args[addrlo_idx + 1]);
} }
tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], addrlo);
args[addrlo_idx]);
if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], datahi); tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], datahi);
} }
@ -1163,7 +1154,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGMemOp memop)
*label_ptr |= INSN_OFF19((unsigned long)s->code_ptr - *label_ptr |= INSN_OFF19((unsigned long)s->code_ptr -
(unsigned long)label_ptr); (unsigned long)label_ptr);
#else #else
addr_reg = args[addrlo_idx];
if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) { if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) {
tcg_out_arithi(s, TCG_REG_T1, addr_reg, 0, SHIFT_SRL); tcg_out_arithi(s, TCG_REG_T1, addr_reg, 0, SHIFT_SRL);
addr_reg = TCG_REG_T1; addr_reg = TCG_REG_T1;