target-microblaze: Convert endi to a CPU property
Originally the endi PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@ -70,7 +70,6 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
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env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
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/* setup pvr to match kernel setting */
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env->pvr.regs[0] |= PVR0_ENDI;
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env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
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env->pvr.regs[4] = 0xc56b8000;
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env->pvr.regs[5] = 0xc56be000;
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@ -99,6 +98,7 @@ petalogix_ml605_init(MachineState *machine)
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object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
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object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
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&error_abort);
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object_property_set_bool(OBJECT(cpu), true, "endianness", &error_abort);
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object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
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/* Attach emulated BRAM through the LMB. */
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@ -66,6 +66,7 @@ typedef struct MicroBlazeCPU {
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uint8_t use_fpu;
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bool use_mmu;
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bool dcache_writeback;
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bool endi;
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} cfg;
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CPUMBState env;
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@ -114,7 +114,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
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env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
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(cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
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(cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0);
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(cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
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(cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
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env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
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(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
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@ -174,6 +175,7 @@ static Property mb_properties[] = {
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DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
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DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
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false),
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DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -124,7 +124,7 @@ typedef struct CPUMBState CPUMBState;
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#define PVR0_USE_DCACHE_MASK 0x01000000
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#define PVR0_USE_MMU_MASK 0x00800000
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#define PVR0_USE_BTC 0x00400000
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#define PVR0_ENDI 0x00200000
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#define PVR0_ENDI_MASK 0x00200000
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#define PVR0_FAULT 0x00100000
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#define PVR0_VERSION_MASK 0x0000FF00
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#define PVR0_USER1_MASK 0x000000FF
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