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target-i386: Tidy extend + move

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For the known MO_32/MO_64 cases, we don't need to extend a 32-bit temp
into a 64-bit temp before storing into the hardware register.

We do need the extension for the MO_8/MO_16 cases, in order for the
deposit_tl operation to work, so leave those alone.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2013-11-05 11:31:34 +10:00
parent d5601ad023
commit a7fbcbe538
1 changed files with 5 additions and 9 deletions
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14
target-i386/translate.c
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@ -3538,16 +3538,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,xmm_regs[rm])); offsetof(CPUX86State,xmm_regs[rm]));
gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0); gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32);
gen_op_mov_reg_T0(MO_32, reg);
break; break;
case 0x150: /* movmskpd */ case 0x150: /* movmskpd */
rm = (modrm & 7) | REX_B(s); rm = (modrm & 7) | REX_B(s);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,xmm_regs[rm])); offsetof(CPUX86State,xmm_regs[rm]));
gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0); gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32);
gen_op_mov_reg_T0(MO_32, reg);
break; break;
case 0x02a: /* cvtpi2ps */ case 0x02a: /* cvtpi2ps */
case 0x12a: /* cvtpi2pd */ case 0x12a: /* cvtpi2pd */
@ -3731,9 +3729,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx)); tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_env, cpu_ptr0); gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_env, cpu_ptr0);
} }
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
reg = ((modrm >> 3) & 7) | rex_r; reg = ((modrm >> 3) & 7) | rex_r;
gen_op_mov_reg_T0(MO_32, reg); tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32);
break; break;
case 0x138: case 0x138:
@ -4229,8 +4226,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3))); xmm_regs[reg].XMM_L(val & 3)));
if (mod == 3) { if (mod == 3) {
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); tcg_gen_extu_i32_tl(cpu_regs[rm], cpu_tmp2_i32);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else { } else {
tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
s->mem_index, MO_LEUL); s->mem_index, MO_LEUL);
@ -4241,7 +4237,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(val & 1))); xmm_regs[reg].XMM_Q(val & 1)));
if (mod == 3) { if (mod == 3) {
gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64); tcg_gen_mov_i64(cpu_regs[rm], cpu_tmp1_i64);
} else { } else {
tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0,
s->mem_index, MO_LEQ); s->mem_index, MO_LEQ);