mirror of https://gitlab.com/qemu-project/qemu
target/arm: Hoist finalize_memop out of do_gpr_{ld, st}
We are going to need the complete memop beforehand, so let's not compute it twice. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230530191438.411344-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -838,7 +838,6 @@ static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source,
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unsigned int iss_srt,
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unsigned int iss_srt,
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bool iss_sf, bool iss_ar)
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bool iss_sf, bool iss_ar)
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{
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{
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memop = finalize_memop(s, memop);
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tcg_gen_qemu_st_i64(source, tcg_addr, memidx, memop);
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tcg_gen_qemu_st_i64(source, tcg_addr, memidx, memop);
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if (iss_valid) {
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if (iss_valid) {
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@ -873,7 +872,6 @@ static void do_gpr_ld_memidx(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
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bool iss_valid, unsigned int iss_srt,
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bool iss_valid, unsigned int iss_srt,
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bool iss_sf, bool iss_ar)
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bool iss_sf, bool iss_ar)
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{
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{
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memop = finalize_memop(s, memop);
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tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop);
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tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop);
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if (extend && (memop & MO_SIGN)) {
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if (extend && (memop & MO_SIGN)) {
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@ -2625,6 +2623,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
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int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr;
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int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr;
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int size = extract32(insn, 30, 2);
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int size = extract32(insn, 30, 2);
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TCGv_i64 clean_addr;
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TCGv_i64 clean_addr;
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MemOp memop;
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switch (o2_L_o1_o0) {
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switch (o2_L_o1_o0) {
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case 0x0: /* STXR */
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case 0x0: /* STXR */
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@ -2661,10 +2660,11 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
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gen_check_sp_alignment(s);
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gen_check_sp_alignment(s);
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}
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}
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
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/* TODO: ARMv8.4-LSE SCTLR.nAA */
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memop = finalize_memop(s, size | MO_ALIGN);
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
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true, rn != 31, size);
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true, rn != 31, size);
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/* TODO: ARMv8.4-LSE SCTLR.nAA */
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do_gpr_st(s, cpu_reg(s, rt), clean_addr, memop, true, rt,
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do_gpr_st(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, true, rt,
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disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
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disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
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return;
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return;
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@ -2679,10 +2679,11 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
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if (rn == 31) {
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if (rn == 31) {
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gen_check_sp_alignment(s);
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gen_check_sp_alignment(s);
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}
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}
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/* TODO: ARMv8.4-LSE SCTLR.nAA */
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memop = finalize_memop(s, size | MO_ALIGN);
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
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false, rn != 31, size);
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false, rn != 31, size);
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/* TODO: ARMv8.4-LSE SCTLR.nAA */
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do_gpr_ld(s, cpu_reg(s, rt), clean_addr, memop, false, true,
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do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, false, true,
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rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
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rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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return;
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return;
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@ -2790,9 +2791,9 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
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} else {
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} else {
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/* Only unsigned 32bit loads target 32bit registers. */
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/* Only unsigned 32bit loads target 32bit registers. */
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bool iss_sf = opc != 0;
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bool iss_sf = opc != 0;
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MemOp memop = finalize_memop(s, size + is_signed * MO_SIGN);
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do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN,
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do_gpr_ld(s, tcg_rt, clean_addr, memop, false, true, rt, iss_sf, false);
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false, true, rt, iss_sf, false);
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}
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}
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}
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}
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@ -3046,7 +3047,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
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bool post_index;
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bool post_index;
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bool writeback;
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bool writeback;
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int memidx;
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int memidx;
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MemOp memop;
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TCGv_i64 clean_addr, dirty_addr;
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TCGv_i64 clean_addr, dirty_addr;
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if (is_vector) {
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if (is_vector) {
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@ -3073,7 +3074,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
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return;
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return;
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}
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}
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is_store = (opc == 0);
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is_store = (opc == 0);
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is_signed = extract32(opc, 1, 1);
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is_signed = !is_store && extract32(opc, 1, 1);
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is_extended = (size < 3) && extract32(opc, 0, 1);
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is_extended = (size < 3) && extract32(opc, 0, 1);
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}
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}
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@ -3107,6 +3108,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
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}
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}
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memidx = is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s);
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memidx = is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s);
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memop = finalize_memop(s, size + is_signed * MO_SIGN);
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clean_addr = gen_mte_check1_mmuidx(s, dirty_addr, is_store,
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clean_addr = gen_mte_check1_mmuidx(s, dirty_addr, is_store,
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writeback || rn != 31,
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writeback || rn != 31,
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size, is_unpriv, memidx);
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size, is_unpriv, memidx);
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@ -3122,10 +3125,10 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
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bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
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bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
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if (is_store) {
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if (is_store) {
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do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx,
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do_gpr_st_memidx(s, tcg_rt, clean_addr, memop, memidx,
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iss_valid, rt, iss_sf, false);
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iss_valid, rt, iss_sf, false);
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} else {
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} else {
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do_gpr_ld_memidx(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN,
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do_gpr_ld_memidx(s, tcg_rt, clean_addr, memop,
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is_extended, memidx,
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is_extended, memidx,
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iss_valid, rt, iss_sf, false);
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iss_valid, rt, iss_sf, false);
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}
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}
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@ -3174,8 +3177,8 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
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bool is_signed = false;
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bool is_signed = false;
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bool is_store = false;
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bool is_store = false;
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bool is_extended = false;
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bool is_extended = false;
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TCGv_i64 tcg_rm, clean_addr, dirty_addr;
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TCGv_i64 tcg_rm, clean_addr, dirty_addr;
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MemOp memop;
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if (extract32(opt, 1, 1) == 0) {
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if (extract32(opt, 1, 1) == 0) {
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unallocated_encoding(s);
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unallocated_encoding(s);
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@ -3202,7 +3205,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
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return;
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return;
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}
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}
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is_store = (opc == 0);
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is_store = (opc == 0);
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is_signed = extract32(opc, 1, 1);
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is_signed = !is_store && extract32(opc, 1, 1);
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is_extended = (size < 3) && extract32(opc, 0, 1);
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is_extended = (size < 3) && extract32(opc, 0, 1);
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}
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}
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@ -3215,6 +3218,8 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
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ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0);
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ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0);
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tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm);
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tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm);
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memop = finalize_memop(s, size + is_signed * MO_SIGN);
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clean_addr = gen_mte_check1(s, dirty_addr, is_store, true, size);
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clean_addr = gen_mte_check1(s, dirty_addr, is_store, true, size);
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if (is_vector) {
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if (is_vector) {
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@ -3226,11 +3231,12 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
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} else {
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} else {
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TCGv_i64 tcg_rt = cpu_reg(s, rt);
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TCGv_i64 tcg_rt = cpu_reg(s, rt);
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bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
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bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
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if (is_store) {
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if (is_store) {
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do_gpr_st(s, tcg_rt, clean_addr, size,
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do_gpr_st(s, tcg_rt, clean_addr, memop,
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true, rt, iss_sf, false);
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true, rt, iss_sf, false);
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} else {
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} else {
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do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN,
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do_gpr_ld(s, tcg_rt, clean_addr, memop,
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is_extended, true, rt, iss_sf, false);
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is_extended, true, rt, iss_sf, false);
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}
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}
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}
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}
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@ -3262,12 +3268,11 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
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int rn = extract32(insn, 5, 5);
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int rn = extract32(insn, 5, 5);
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unsigned int imm12 = extract32(insn, 10, 12);
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unsigned int imm12 = extract32(insn, 10, 12);
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unsigned int offset;
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unsigned int offset;
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TCGv_i64 clean_addr, dirty_addr;
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TCGv_i64 clean_addr, dirty_addr;
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bool is_store;
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bool is_store;
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bool is_signed = false;
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bool is_signed = false;
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bool is_extended = false;
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bool is_extended = false;
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MemOp memop;
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if (is_vector) {
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if (is_vector) {
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size |= (opc & 2) << 1;
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size |= (opc & 2) << 1;
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@ -3289,7 +3294,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
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return;
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return;
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}
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}
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is_store = (opc == 0);
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is_store = (opc == 0);
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is_signed = extract32(opc, 1, 1);
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is_signed = !is_store && extract32(opc, 1, 1);
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is_extended = (size < 3) && extract32(opc, 0, 1);
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is_extended = (size < 3) && extract32(opc, 0, 1);
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}
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}
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@ -3299,6 +3304,8 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
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dirty_addr = read_cpu_reg_sp(s, rn, 1);
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dirty_addr = read_cpu_reg_sp(s, rn, 1);
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offset = imm12 << size;
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offset = imm12 << size;
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tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
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tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
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memop = finalize_memop(s, size + is_signed * MO_SIGN);
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clean_addr = gen_mte_check1(s, dirty_addr, is_store, rn != 31, size);
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clean_addr = gen_mte_check1(s, dirty_addr, is_store, rn != 31, size);
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if (is_vector) {
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if (is_vector) {
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@ -3311,10 +3318,9 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
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TCGv_i64 tcg_rt = cpu_reg(s, rt);
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TCGv_i64 tcg_rt = cpu_reg(s, rt);
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bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
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bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
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if (is_store) {
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if (is_store) {
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do_gpr_st(s, tcg_rt, clean_addr, size,
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do_gpr_st(s, tcg_rt, clean_addr, memop, true, rt, iss_sf, false);
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true, rt, iss_sf, false);
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} else {
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} else {
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do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN,
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do_gpr_ld(s, tcg_rt, clean_addr, memop,
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is_extended, true, rt, iss_sf, false);
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is_extended, true, rt, iss_sf, false);
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}
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}
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}
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}
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@ -3344,7 +3350,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
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bool a = extract32(insn, 23, 1);
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bool a = extract32(insn, 23, 1);
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TCGv_i64 tcg_rs, tcg_rt, clean_addr;
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TCGv_i64 tcg_rs, tcg_rt, clean_addr;
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AtomicThreeOpFn *fn = NULL;
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AtomicThreeOpFn *fn = NULL;
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MemOp mop = s->be_data | size | MO_ALIGN;
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MemOp mop = finalize_memop(s, size | MO_ALIGN);
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if (is_vector || !dc_isar_feature(aa64_atomics, s)) {
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if (is_vector || !dc_isar_feature(aa64_atomics, s)) {
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unallocated_encoding(s);
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unallocated_encoding(s);
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@ -3405,7 +3411,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
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* full load-acquire (we only need "load-acquire processor consistent"),
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* full load-acquire (we only need "load-acquire processor consistent"),
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* but we choose to implement them as full LDAQ.
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* but we choose to implement them as full LDAQ.
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*/
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*/
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do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false,
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do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop, false,
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true, rt, disas_ldst_compute_iss_sf(size, false, 0), true);
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true, rt, disas_ldst_compute_iss_sf(size, false, 0), true);
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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return;
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return;
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@ -3451,6 +3457,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn,
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bool use_key_a = !extract32(insn, 23, 1);
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bool use_key_a = !extract32(insn, 23, 1);
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int offset;
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int offset;
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TCGv_i64 clean_addr, dirty_addr, tcg_rt;
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TCGv_i64 clean_addr, dirty_addr, tcg_rt;
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MemOp memop;
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if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) {
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if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) {
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unallocated_encoding(s);
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unallocated_encoding(s);
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@ -3477,12 +3484,14 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn,
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offset = sextract32(offset << size, 0, 10 + size);
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offset = sextract32(offset << size, 0, 10 + size);
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tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
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tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
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memop = finalize_memop(s, size);
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/* Note that "clean" and "dirty" here refer to TBI not PAC. */
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/* Note that "clean" and "dirty" here refer to TBI not PAC. */
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clean_addr = gen_mte_check1(s, dirty_addr, false,
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clean_addr = gen_mte_check1(s, dirty_addr, false,
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is_wback || rn != 31, size);
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is_wback || rn != 31, size);
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tcg_rt = cpu_reg(s, rt);
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tcg_rt = cpu_reg(s, rt);
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do_gpr_ld(s, tcg_rt, clean_addr, size,
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do_gpr_ld(s, tcg_rt, clean_addr, memop,
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/* extend */ false, /* iss_valid */ !is_wback,
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/* extend */ false, /* iss_valid */ !is_wback,
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/* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false);
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/* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false);
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@ -3524,7 +3533,7 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn)
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||||||
}
|
}
|
||||||
|
|
||||||
/* TODO: ARMv8.4-LSE SCTLR.nAA */
|
/* TODO: ARMv8.4-LSE SCTLR.nAA */
|
||||||
mop = size | MO_ALIGN;
|
mop = finalize_memop(s, size | MO_ALIGN);
|
||||||
|
|
||||||
switch (opc) {
|
switch (opc) {
|
||||||
case 0: /* STLURB */
|
case 0: /* STLURB */
|
||||||
|
|
Loading…
Reference in New Issue