target/arm: Convert load reg (literal) group to decodetree
Convert the "Load register (literal)" instruction class to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-11-peter.maydell@linaro.org
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@ -252,3 +252,16 @@ LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP
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CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2
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CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2
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# CAS, CASA, CASAL, CASL
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# CAS, CASA, CASAL, CASL
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CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5
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CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5
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&ldlit rt imm sz sign
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@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19
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LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0
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LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0
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LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1
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LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0
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LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0
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LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0
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# PRFM
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NOP 11 011 0 00 ------------------- -----
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@ -2787,62 +2787,33 @@ static bool trans_CAS(DisasContext *s, arg_CAS *a)
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return true;
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return true;
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}
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}
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/*
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static bool trans_LD_lit(DisasContext *s, arg_ldlit *a)
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* Load register (literal)
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*
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* 31 30 29 27 26 25 24 23 5 4 0
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* +-----+-------+---+-----+-------------------+-------+
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* | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
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* +-----+-------+---+-----+-------------------+-------+
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*
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* V: 1 -> vector (simd/fp)
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* opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
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* 10-> 32 bit signed, 11 -> prefetch
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* opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
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*/
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static void disas_ld_lit(DisasContext *s, uint32_t insn)
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{
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{
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int rt = extract32(insn, 0, 5);
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bool iss_sf = ldst_iss_sf(a->sz, a->sign, false);
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int64_t imm = sextract32(insn, 5, 19) << 2;
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TCGv_i64 tcg_rt = cpu_reg(s, a->rt);
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bool is_vector = extract32(insn, 26, 1);
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TCGv_i64 clean_addr = tcg_temp_new_i64();
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int opc = extract32(insn, 30, 2);
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MemOp memop = finalize_memop(s, a->sz + a->sign * MO_SIGN);
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bool is_signed = false;
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int size = 2;
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gen_pc_plus_diff(s, clean_addr, a->imm);
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TCGv_i64 tcg_rt, clean_addr;
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do_gpr_ld(s, tcg_rt, clean_addr, memop,
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false, true, a->rt, iss_sf, false);
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return true;
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}
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static bool trans_LD_lit_v(DisasContext *s, arg_ldlit *a)
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{
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/* Load register (literal), vector version */
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TCGv_i64 clean_addr;
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MemOp memop;
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MemOp memop;
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if (is_vector) {
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if (!fp_access_check(s)) {
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if (opc == 3) {
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return true;
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unallocated_encoding(s);
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return;
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}
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size = 2 + opc;
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if (!fp_access_check(s)) {
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return;
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}
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memop = finalize_memop_asimd(s, size);
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} else {
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if (opc == 3) {
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/* PRFM (literal) : prefetch */
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return;
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}
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size = 2 + extract32(opc, 0, 1);
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is_signed = extract32(opc, 1, 1);
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memop = finalize_memop(s, size + is_signed * MO_SIGN);
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}
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}
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memop = finalize_memop_asimd(s, a->sz);
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tcg_rt = cpu_reg(s, rt);
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clean_addr = tcg_temp_new_i64();
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clean_addr = tcg_temp_new_i64();
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gen_pc_plus_diff(s, clean_addr, imm);
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gen_pc_plus_diff(s, clean_addr, a->imm);
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do_fp_ld(s, a->rt, clean_addr, memop);
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if (is_vector) {
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return true;
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do_fp_ld(s, rt, clean_addr, memop);
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} else {
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/* Only unsigned 32bit loads target 32bit registers. */
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bool iss_sf = opc != 0;
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do_gpr_ld(s, tcg_rt, clean_addr, memop, false, true, rt, iss_sf, false);
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}
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}
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}
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/*
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/*
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@ -4213,9 +4184,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
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static void disas_ldst(DisasContext *s, uint32_t insn)
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static void disas_ldst(DisasContext *s, uint32_t insn)
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{
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{
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switch (extract32(insn, 24, 6)) {
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switch (extract32(insn, 24, 6)) {
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case 0x18: case 0x1c: /* Load register (literal) */
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disas_ld_lit(s, insn);
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break;
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case 0x28: case 0x29:
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case 0x28: case 0x29:
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case 0x2c: case 0x2d: /* Load/store pair (all forms) */
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case 0x2c: case 0x2d: /* Load/store pair (all forms) */
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disas_ldst_pair(s, insn);
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disas_ldst_pair(s, insn);
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