mips: malta/boston: replace cpu_model with cpu_type
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1507211474-188400-37-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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@ -437,7 +437,6 @@ static void boston_mach_init(MachineState *machine)
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DeviceState *dev;
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BostonState *s;
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Error *err = NULL;
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const char *cpu_model;
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MemoryRegion *flash, *ddr, *ddr_low_alias, *lcd, *platreg;
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MemoryRegion *sys_mem = get_system_memory();
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XilinxPCIEHost *pcie2;
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@ -453,25 +452,24 @@ static void boston_mach_init(MachineState *machine)
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exit(1);
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}
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cpu_model = machine->cpu_model ?: "I6400";
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dev = qdev_create(NULL, TYPE_MIPS_BOSTON);
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qdev_init_nofail(dev);
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s = BOSTON(dev);
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s->mach = machine;
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if (!cpu_supports_cps_smp(cpu_model)) {
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if (!cpu_supports_cps_smp(machine->cpu_type)) {
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error_report("Boston requires CPUs which support CPS");
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exit(1);
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}
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is_64b = cpu_supports_isa(cpu_model, ISA_MIPS64);
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is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64);
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s->cps = MIPS_CPS(object_new(TYPE_MIPS_CPS));
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qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
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object_property_set_str(OBJECT(s->cps), cpu_model, "cpu-model", &err);
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object_property_set_str(OBJECT(s->cps), machine->cpu_type, "cpu-type",
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&err);
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object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
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object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
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@ -571,6 +569,7 @@ static void boston_mach_class_init(MachineClass *mc)
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mc->block_default_type = IF_IDE;
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mc->default_ram_size = 1 * G_BYTE;
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mc->max_cpus = 16;
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mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400");
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}
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DEFINE_MACHINE("boston", boston_mach_class_init)
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@ -71,7 +71,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
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bool itu_present = false;
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for (i = 0; i < s->num_vp; i++) {
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cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, s->cpu_model));
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cpu = MIPS_CPU(cpu_create(s->cpu_type));
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/* Init internal devices */
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cpu_mips_irq_init_cpu(cpu);
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@ -160,7 +160,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
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static Property mips_cps_properties[] = {
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DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
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DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
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DEFINE_PROP_STRING("cpu-model", MIPSCPSState, cpu_model),
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DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type),
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DEFINE_PROP_END_OF_LIST()
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};
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@ -923,7 +923,7 @@ static void main_cpu_reset(void *opaque)
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}
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}
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static void create_cpu_without_cps(const char *cpu_model,
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static void create_cpu_without_cps(const char *cpu_type,
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qemu_irq *cbus_irq, qemu_irq *i8259_irq)
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{
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CPUMIPSState *env;
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@ -931,7 +931,7 @@ static void create_cpu_without_cps(const char *cpu_model,
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int i;
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for (i = 0; i < smp_cpus; i++) {
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cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model));
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cpu = MIPS_CPU(cpu_create(cpu_type));
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/* Init internal devices */
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cpu_mips_irq_init_cpu(cpu);
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@ -945,7 +945,7 @@ static void create_cpu_without_cps(const char *cpu_model,
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*cbus_irq = env->irq[4];
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}
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static void create_cps(MaltaState *s, const char *cpu_model,
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static void create_cps(MaltaState *s, const char *cpu_type,
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qemu_irq *cbus_irq, qemu_irq *i8259_irq)
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{
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Error *err = NULL;
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@ -953,7 +953,7 @@ static void create_cps(MaltaState *s, const char *cpu_model,
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s->cps = MIPS_CPS(object_new(TYPE_MIPS_CPS));
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qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
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object_property_set_str(OBJECT(s->cps), cpu_model, "cpu-model", &err);
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object_property_set_str(OBJECT(s->cps), cpu_type, "cpu-type", &err);
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object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
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object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
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if (err != NULL) {
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@ -967,21 +967,13 @@ static void create_cps(MaltaState *s, const char *cpu_model,
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*cbus_irq = NULL;
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}
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static void create_cpu(MaltaState *s, const char *cpu_model,
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static void mips_create_cpu(MaltaState *s, const char *cpu_type,
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qemu_irq *cbus_irq, qemu_irq *i8259_irq)
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{
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if (cpu_model == NULL) {
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#ifdef TARGET_MIPS64
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cpu_model = "20Kc";
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#else
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cpu_model = "24Kf";
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#endif
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}
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if ((smp_cpus > 1) && cpu_supports_cps_smp(cpu_model)) {
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create_cps(s, cpu_model, cbus_irq, i8259_irq);
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if ((smp_cpus > 1) && cpu_supports_cps_smp(cpu_type)) {
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create_cps(s, cpu_type, cbus_irq, i8259_irq);
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} else {
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create_cpu_without_cps(cpu_model, cbus_irq, i8259_irq);
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create_cpu_without_cps(cpu_type, cbus_irq, i8259_irq);
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}
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}
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@ -1038,7 +1030,7 @@ void mips_malta_init(MachineState *machine)
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}
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/* create CPU */
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create_cpu(s, machine->cpu_model, &cbus_irq, &i8259_irq);
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mips_create_cpu(s, machine->cpu_type, &cbus_irq, &i8259_irq);
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/* allocate RAM */
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if (ram_size > (2048u << 20)) {
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@ -1264,6 +1256,11 @@ static void mips_malta_machine_init(MachineClass *mc)
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mc->block_default_type = IF_IDE;
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mc->max_cpus = 16;
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mc->is_default = 1;
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#ifdef TARGET_MIPS64
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mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc");
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#else
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mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
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#endif
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}
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DEFINE_MACHINE("malta", mips_malta_machine_init)
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@ -34,7 +34,7 @@ typedef struct MIPSCPSState {
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uint32_t num_vp;
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uint32_t num_irq;
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char *cpu_model;
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char *cpu_type;
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MemoryRegion container;
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MIPSGCRState gcr;
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@ -154,7 +154,7 @@ static void mips_cpu_initfn(Object *obj)
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static char *mips_cpu_type_name(const char *cpu_model)
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{
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return g_strdup_printf("%s-" TYPE_MIPS_CPU, cpu_model);
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return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model);
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}
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static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
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@ -740,8 +740,12 @@ enum {
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int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
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#define cpu_init(cpu_model) cpu_generic_init(TYPE_MIPS_CPU, cpu_model)
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bool cpu_supports_cps_smp(const char *cpu_model);
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bool cpu_supports_isa(const char *cpu_model, unsigned int isa);
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#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
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#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
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bool cpu_supports_cps_smp(const char *cpu_type);
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bool cpu_supports_isa(const char *cpu_type, unsigned int isa);
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void cpu_set_exception_base(int vp_index, target_ulong address);
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/* mips_int.c */
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@ -20512,24 +20512,16 @@ void cpu_mips_realize_env(CPUMIPSState *env)
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mvp_init(env, env->cpu_model);
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}
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bool cpu_supports_cps_smp(const char *cpu_model)
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bool cpu_supports_cps_smp(const char *cpu_type)
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{
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const mips_def_t *def = cpu_mips_find_by_name(cpu_model);
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if (!def) {
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return false;
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const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
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return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
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}
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return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
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}
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bool cpu_supports_isa(const char *cpu_model, unsigned int isa)
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bool cpu_supports_isa(const char *cpu_type, unsigned int isa)
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{
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const mips_def_t *def = cpu_mips_find_by_name(cpu_model);
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if (!def) {
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return false;
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}
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return (def->insn_flags & isa) != 0;
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const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
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return (mcc->cpu_def->insn_flags & isa) != 0;
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}
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void cpu_set_exception_base(int vp_index, target_ulong address)
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@ -755,18 +755,6 @@ const mips_def_t mips_defs[] =
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};
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const int mips_defs_number = ARRAY_SIZE(mips_defs);
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static const mips_def_t *cpu_mips_find_by_name (const char *name)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
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if (strcasecmp(name, mips_defs[i].name) == 0) {
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return &mips_defs[i];
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}
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}
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return NULL;
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}
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void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
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{
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int i;
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