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PPC: e500: Fix MMUCSR0 emulation

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A  "mtspr SPRMMUCSR0, reg"  always flushed TLB0,
because it passed the SPR number 0x3f4 to the flush routine.
But we want to flush either TLB0 or TBL1 depending on the GPR value.

Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
[agraf: change subject line, fix TCGv size mismatch]
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alex Zuepke 2014-05-28 19:25:36 +02:00 committed by Alexander Graf
parent 1b8eceee28
commit a721d390b3
3 changed files with 3 additions and 5 deletions
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2
target-ppc/helper.h
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@ -539,7 +539,7 @@ DEF_HELPER_2(booke206_tlbivax, void, env, tl)
DEF_HELPER_2(booke206_tlbilx0, void, env, tl)
DEF_HELPER_2(booke206_tlbilx1, void, env, tl)
DEF_HELPER_2(booke206_tlbilx3, void, env, tl)
DEF_HELPER_2(booke206_tlbflush, void, env, i32)
DEF_HELPER_2(booke206_tlbflush, void, env, tl)
DEF_HELPER_3(booke_setpid, void, env, i32, tl)
DEF_HELPER_2(6xx_tlbd, void, env, tl)
DEF_HELPER_2(6xx_tlbi, void, env, tl)

2
target-ppc/mmu_helper.c
View File

@ -2886,7 +2886,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
tlb_flush(CPU(cpu), 1);
}
void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type)
void helper_booke206_tlbflush(CPUPPCState *env, target_ulong type)
{
int flags = 0;

4
target-ppc/translate_init.c
View File

@ -1466,9 +1466,7 @@ static void spr_write_e500_l1csr1(void *opaque, int sprn, int gprn)
static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(sprn);
gen_helper_booke206_tlbflush(cpu_env, t0);
tcg_temp_free_i32(t0);
gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
}
static void spr_write_booke_pid (void *opaque, int sprn, int gprn)