target/ppc: Moved XVTSTDC[DS]P to decodetree
Moved XVTSTDCSP and XVTSTDCDP to decodetree an restructured the helper to be simpler and do all decoding in the decodetree (so XB, XT and DCMX are all calculated outside the helper). Obs: The tests in this one are slightly different, these are the sum of these instructions with all possible immediate and those instructions are repeated 10 times. xvtstdcsp: rept loop master patch 8 12500 2,76402100 2,70699100 (-2.1%) 25 4000 2,64867100 2,67884100 (+1.1%) 100 1000 2,73806300 2,78701000 (+1.8%) 500 200 3,44666500 3,61027600 (+4.7%) 2500 40 5,85790200 6,47475500 (+10.5%) 8000 12 15,22102100 17,46062900 (+14.7%) xvtstdcdp: rept loop master patch 8 12500 2,11818000 1,61065300 (-24.0%) 25 4000 2,04573400 1,60132200 (-21.7%) 100 1000 2,13834100 1,69988100 (-20.5%) 500 200 2,73977000 2,48631700 (-9.3%) 2500 40 5,05067000 5,25914100 (+4.1%) 8000 12 14,60507800 15,93704900 (+9.1%) Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221019125040.48028-11-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Lucas Mateus Castro (alqotel)
Daniel Henrique Barboza
parent
95a89d3118
commit
a70a524710
@ -3295,11 +3295,46 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
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} \
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}
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VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX, 0)
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VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX, 0)
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VSX_TEST_DC(xststdcdp, 1, xB(opcode), float64, VsrD(0), VsrD(0), 0, 1)
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VSX_TEST_DC(xststdcqp, 1, (rB(opcode) + 32), float128, f128, VsrD(0), 0, 1)
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#define VSX_TSTDC(tp) \
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static int32_t tp##_tstdc(tp b, uint32_t dcmx) \
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{ \
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uint32_t match = 0; \
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uint32_t sign = tp##_is_neg(b); \
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if (tp##_is_any_nan(b)) { \
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match = extract32(dcmx, 6, 1); \
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} else if (tp##_is_infinity(b)) { \
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match = extract32(dcmx, 4 + !sign, 1); \
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} else if (tp##_is_zero(b)) { \
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match = extract32(dcmx, 2 + !sign, 1); \
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} else if (tp##_is_zero_or_denormal(b)) { \
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match = extract32(dcmx, 0 + !sign, 1); \
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} \
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return (match != 0); \
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}
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VSX_TSTDC(float32)
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VSX_TSTDC(float64)
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#undef VSX_TSTDC
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void helper_XVTSTDCDP(ppc_vsr_t *t, ppc_vsr_t *b, uint64_t dcmx, uint32_t v)
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{
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int i;
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for (i = 0; i < 2; i++) {
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t->s64[i] = (int64_t)-float64_tstdc(b->f64[i], dcmx);
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}
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}
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void helper_XVTSTDCSP(ppc_vsr_t *t, ppc_vsr_t *b, uint64_t dcmx, uint32_t v)
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{
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int i;
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for (i = 0; i < 4; i++) {
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t->s32[i] = (int32_t)-float32_tstdc(b->f32[i], dcmx);
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}
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}
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void helper_xststdcsp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb)
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{
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uint32_t dcmx, sign, exp;
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@ -517,8 +517,8 @@ DEF_HELPER_3(xvcvsxdsp, void, env, vsr, vsr)
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DEF_HELPER_3(xvcvuxdsp, void, env, vsr, vsr)
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DEF_HELPER_3(xvcvsxwsp, void, env, vsr, vsr)
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DEF_HELPER_3(xvcvuxwsp, void, env, vsr, vsr)
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DEF_HELPER_2(xvtstdcsp, void, env, i32)
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DEF_HELPER_2(xvtstdcdp, void, env, i32)
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DEF_HELPER_FLAGS_4(XVTSTDCSP, TCG_CALL_NO_RWG, void, vsr, vsr, i64, i32)
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DEF_HELPER_FLAGS_4(XVTSTDCDP, TCG_CALL_NO_RWG, void, vsr, vsr, i64, i32)
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DEF_HELPER_3(xvrspi, void, env, vsr, vsr)
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DEF_HELPER_3(xvrspic, void, env, vsr, vsr)
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DEF_HELPER_3(xvrspim, void, env, vsr, vsr)
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@ -199,6 +199,9 @@
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@XX2_uim4 ...... ..... . uim:4 ..... ......... .. &XX2_uim xt=%xx_xt xb=%xx_xb
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%xx_uim7 6:1 2:1 16:5
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@XX2_uim7 ...... ..... ..... ..... .... . ... . .. &XX2_uim xt=%xx_xt xb=%xx_xb uim=%xx_uim7
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&XX2_bf_xb bf xb
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@XX2_bf_xb ...... bf:3 .. ..... ..... ......... . . &XX2_bf_xb xb=%xx_xb
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@ -848,6 +851,8 @@ XSCVSPDPN 111100 ..... ----- ..... 101001011 .. @XX2
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## VSX Binary Floating-Point Math Support Instructions
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XVXSIGSP 111100 ..... 01001 ..... 111011011 .. @XX2
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XVTSTDCDP 111100 ..... ..... ..... 1111 . 101 ... @XX2_uim7
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XVTSTDCSP 111100 ..... ..... ..... 1101 . 101 ... @XX2_uim7
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## VSX Vector Test Least-Significant Bit by Byte Instruction
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@ -630,6 +630,8 @@ static void gen_mtvsrws(DisasContext *ctx)
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#define OP_CPSGN 4
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#define SGN_MASK_DP 0x8000000000000000ull
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#define SGN_MASK_SP 0x8000000080000000ull
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#define EXP_MASK_DP 0x7FF0000000000000ull
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#define EXP_MASK_SP 0x7F8000007F800000ull
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#define VSX_SCALAR_MOVE(name, op, sgn_mask) \
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static void glue(gen_, name)(DisasContext *ctx) \
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@ -1110,6 +1112,30 @@ GEN_VSX_HELPER_X2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300)
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GEN_VSX_HELPER_R2(xscvsdqp, 0x04, 0x1A, 0x0A, PPC2_ISA300)
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GEN_VSX_HELPER_X2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
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static bool do_xvtstdc(DisasContext *ctx, arg_XX2_uim *a, unsigned vece)
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{
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static const GVecGen2i op[] = {
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{
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.fnoi = gen_helper_XVTSTDCSP,
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.vece = MO_32
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},
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{
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.fnoi = gen_helper_XVTSTDCDP,
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.vece = MO_64
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},
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};
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REQUIRE_VSX(ctx);
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tcg_gen_gvec_2i(vsr_full_offset(a->xt), vsr_full_offset(a->xb),
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16, 16, (int32_t)(a->uim), &op[vece - MO_32]);
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return true;
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}
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TRANS_FLAGS2(VSX, XVTSTDCSP, do_xvtstdc, MO_32)
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TRANS_FLAGS2(VSX, XVTSTDCDP, do_xvtstdc, MO_64)
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bool trans_XSCVSPDPN(DisasContext *ctx, arg_XX2 *a)
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{
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TCGv_i64 tmp;
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@ -1213,8 +1239,6 @@ GEN_VSX_HELPER_X2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
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GEN_VSX_HELPER_X2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
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GEN_VSX_HELPER_X2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
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GEN_VSX_HELPER_X2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvtstdcsp, 0x14, 0x1A, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvtstdcdp, 0x14, 0x1E, 0, PPC2_VSX)
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static bool trans_XXPERM(DisasContext *ctx, arg_XX3 *a)
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{
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@ -157,14 +157,6 @@ GEN_XX2FORM_EO(xvxexpdp, 0x16, 0x1D, 0x00, PPC2_ISA300),
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GEN_XX2FORM_EO(xvxsigdp, 0x16, 0x1D, 0x01, PPC2_ISA300),
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GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300),
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/* DCMX = bit[25] << 6 | bit[29] << 5 | bit[11:15] */
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#define GEN_XX2FORM_DCMX(name, opc2, opc3, fl2) \
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GEN_XX3FORM(name, opc2, opc3 | 0, fl2), \
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GEN_XX3FORM(name, opc2, opc3 | 1, fl2)
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GEN_XX2FORM_DCMX(xvtstdcdp, 0x14, 0x1E, PPC2_ISA300),
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GEN_XX2FORM_DCMX(xvtstdcsp, 0x14, 0x1A, PPC2_ISA300),
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GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
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GEN_VSX_XFORM_300(xsaddqp, 0x04, 0x00, 0x0),
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GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
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