target/i386: Reorder DisasContext members
Sort all of the single-byte members to the same area of the structure, eliminating 8 bytes of padding. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-29-richard.henderson@linaro.org>
This commit is contained in:
parent
3236c2ade2
commit
a6f62100a8
@ -76,20 +76,24 @@ static TCGv_i64 cpu_bndu[4];
|
|||||||
typedef struct DisasContext {
|
typedef struct DisasContext {
|
||||||
DisasContextBase base;
|
DisasContextBase base;
|
||||||
|
|
||||||
/* current insn context */
|
target_ulong pc; /* pc = eip + cs_base */
|
||||||
int8_t override; /* -1 if no override, else R_CS, R_DS, etc */
|
target_ulong pc_start; /* pc at TB entry */
|
||||||
uint8_t prefix;
|
target_ulong cs_base; /* base of CS segment */
|
||||||
|
|
||||||
MemOp aflag;
|
MemOp aflag;
|
||||||
MemOp dflag;
|
MemOp dflag;
|
||||||
target_ulong pc_start;
|
|
||||||
target_ulong pc; /* pc = eip + cs_base */
|
int8_t override; /* -1 if no override, else R_CS, R_DS, etc */
|
||||||
/* current block context */
|
uint8_t prefix;
|
||||||
target_ulong cs_base; /* base of CS segment */
|
|
||||||
|
|
||||||
#ifndef CONFIG_USER_ONLY
|
#ifndef CONFIG_USER_ONLY
|
||||||
uint8_t cpl; /* code priv level */
|
uint8_t cpl; /* code priv level */
|
||||||
uint8_t iopl; /* i/o priv level */
|
uint8_t iopl; /* i/o priv level */
|
||||||
#endif
|
#endif
|
||||||
|
uint8_t vex_l; /* vex vector length */
|
||||||
|
uint8_t vex_v; /* vex vvvv register, without 1's complement. */
|
||||||
|
uint8_t popl_esp_hack; /* for correct popl with esp base handling */
|
||||||
|
uint8_t rip_offset; /* only used in x86_64, but left for simplicity */
|
||||||
|
|
||||||
#ifdef TARGET_X86_64
|
#ifdef TARGET_X86_64
|
||||||
uint8_t rex_r;
|
uint8_t rex_r;
|
||||||
@ -97,16 +101,13 @@ typedef struct DisasContext {
|
|||||||
uint8_t rex_b;
|
uint8_t rex_b;
|
||||||
bool rex_w;
|
bool rex_w;
|
||||||
#endif
|
#endif
|
||||||
uint8_t vex_l; /* vex vector length */
|
|
||||||
uint8_t vex_v; /* vex vvvv register, without 1's complement. */
|
|
||||||
CCOp cc_op; /* current CC operation */
|
|
||||||
bool cc_op_dirty;
|
|
||||||
bool jmp_opt; /* use direct block chaining for direct jumps */
|
bool jmp_opt; /* use direct block chaining for direct jumps */
|
||||||
bool repz_opt; /* optimize jumps within repz instructions */
|
bool repz_opt; /* optimize jumps within repz instructions */
|
||||||
|
bool cc_op_dirty;
|
||||||
|
|
||||||
|
CCOp cc_op; /* current CC operation */
|
||||||
int mem_index; /* select memory access functions */
|
int mem_index; /* select memory access functions */
|
||||||
uint32_t flags; /* all execution flags */
|
uint32_t flags; /* all execution flags */
|
||||||
uint8_t popl_esp_hack; /* for correct popl with esp base handling */
|
|
||||||
uint8_t rip_offset; /* only used in x86_64, but left for simplicity */
|
|
||||||
int cpuid_features;
|
int cpuid_features;
|
||||||
int cpuid_ext_features;
|
int cpuid_ext_features;
|
||||||
int cpuid_ext2_features;
|
int cpuid_ext2_features;
|
||||||
|
Loading…
Reference in New Issue
Block a user