mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written

Browse Source 
Don't allow the guest to write CNTHCTL_EL2 bits which don't exist.
This is not strictly architecturally required, but it is how we've
tended to implement registers more recently.

In particular, bits [19:18] are only present with FEAT_RME,
and bits [17:12] will only be present with FEAT_ECV.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301183219.2424889-5-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2024-03-07 12:19:02 +00:00
parent c6b0ecb236
commit a681d66e95
1 changed files with 18 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
target/arm/helper.c
View File

@ -2968,6 +2968,24 @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
{
ARMCPU *cpu = env_archcpu(env);
uint32_t oldval = env->cp15.cnthctl_el2;
uint32_t valid_mask =
R_CNTHCTL_EL0PCTEN_E2H1_MASK |
R_CNTHCTL_EL0VCTEN_E2H1_MASK |
R_CNTHCTL_EVNTEN_MASK |
R_CNTHCTL_EVNTDIR_MASK |
R_CNTHCTL_EVNTI_MASK |
R_CNTHCTL_EL0VTEN_MASK |
R_CNTHCTL_EL0PTEN_MASK |
R_CNTHCTL_EL1PCTEN_E2H1_MASK |
R_CNTHCTL_EL1PTEN_MASK;
if (cpu_isar_feature(aa64_rme, cpu)) {
valid_mask |= R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK;
}
/* Clear RES0 bits */
value &= valid_mask;
raw_write(env, ri, value);
if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) {