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target/arm: Implement vector shifted SCVF/UCVF for fp16

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While we have some of the scalar paths for *CVF for fp16,
we failed to decode the fp16 version of these instructions.

Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180502221552.3873-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-05-10 18:10:57 +01:00 committed by Peter Maydell
parent ec7f05fae3
commit a6117fae45
1 changed files with 20 additions and 13 deletions
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33
target/arm/translate-a64.c
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@ -7405,13 +7405,26 @@ static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,
int immh, int immb, int opcode,
int rn, int rd)
{
bool is_double = extract32(immh, 3, 1);
int size = is_double ? MO_64 : MO_32;
int elements;
int size, elements, fracbits;
int immhb = immh << 3 | immb;
int fracbits = (is_double ? 128 : 64) - immhb;
if (!extract32(immh, 2, 2)) {
if (immh & 8) {
size = MO_64;
if (!is_scalar && !is_q) {
unallocated_encoding(s);
return;
}
} else if (immh & 4) {
size = MO_32;
} else if (immh & 2) {
size = MO_16;
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
unallocated_encoding(s);
return;
}
} else {
/* immh == 0 would be a failure of the decode logic */
g_assert(immh == 1);
unallocated_encoding(s);
return;
}
@ -7419,20 +7432,14 @@ static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,
if (is_scalar) {
elements = 1;
} else {
elements = is_double ? 2 : is_q ? 4 : 2;
if (is_double && !is_q) {
unallocated_encoding(s);
return;
}
elements = (8 << is_q) >> size;
}
fracbits = (16 << size) - immhb;
if (!fp_access_check(s)) {
return;
}
/* immh == 0 would be a failure of the decode logic */
g_assert(immh);
handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size);
}