target-arm: Simplify three-register pairwise code
Since we know that the case of (pairwise && q) has been caught earlier, we can simplify the register setup code for each pass in the three-register-same-size Neon loop. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -4328,7 +4328,6 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
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int count;
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int pairwise;
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int u;
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int n;
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uint32_t imm, mask;
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TCGv tmp, tmp2, tmp3, tmp4, tmp5;
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TCGv_i64 tmp64;
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@ -4480,16 +4479,12 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
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if (pairwise) {
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/* Pairwise. */
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if (q)
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n = (pass & 1) * 2;
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else
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n = 0;
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if (pass < q + 1) {
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tmp = neon_load_reg(rn, n);
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tmp2 = neon_load_reg(rn, n + 1);
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if (pass < 1) {
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tmp = neon_load_reg(rn, 0);
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tmp2 = neon_load_reg(rn, 1);
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} else {
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tmp = neon_load_reg(rm, n);
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tmp2 = neon_load_reg(rm, n + 1);
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tmp = neon_load_reg(rm, 0);
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tmp2 = neon_load_reg(rm, 1);
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}
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} else {
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/* Elementwise. */
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@ -5147,6 +5142,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
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/* VMOV, VMVN. */
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tmp = tcg_temp_new_i32();
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if (op == 14 && invert) {
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int n;
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uint32_t val;
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val = 0;
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for (n = 0; n < 4; n++) {
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@ -5575,6 +5571,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
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break;
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case 33: /* VTRN */
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if (size == 2) {
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int n;
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for (n = 0; n < (q ? 4 : 2); n += 2) {
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tmp = neon_load_reg(rm, n);
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tmp2 = neon_load_reg(rd, n + 1);
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@ -5866,7 +5863,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
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}
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} else if ((insn & (1 << 10)) == 0) {
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/* VTBL, VTBX. */
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n = ((insn >> 5) & 0x18) + 8;
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int n = ((insn >> 5) & 0x18) + 8;
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if (insn & (1 << 6)) {
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tmp = neon_load_reg(rd, 0);
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} else {
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