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target-s390x: Don't overuse CPUState

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Scripted conversion:
  sed -i "s/CPUState/CPUS390XState/g" target-s390x/*.[hc]
  sed -i "s/#define CPUS390XState/#define CPUState/" target-s390x/cpu.h

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Andreas Färber 2012-03-14 01:38:22 +01:00
parent 1328c2bf21
commit a4e3ad19d2
5 changed files with 133 additions and 133 deletions
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46
target-s390x/cpu.h
View File

@ -106,7 +106,7 @@ typedef struct CPUS390XState {
} CPUS390XState; } CPUS390XState;
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) static inline void cpu_clone_regs(CPUS390XState *env, target_ulong newsp)
{ {
if (newsp) { if (newsp) {
env->regs[15] = newsp; env->regs[15] = newsp;
@ -233,7 +233,7 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
#define FLAG_MASK_64 (PSW_MASK_64 >> 32) #define FLAG_MASK_64 (PSW_MASK_64 >> 32)
#define FLAG_MASK_32 0x00001000 #define FLAG_MASK_32 0x00001000
static inline int cpu_mmu_index (CPUState *env) static inline int cpu_mmu_index (CPUS390XState *env)
{ {
if (env->psw.mask & PSW_MASK_PSTATE) { if (env->psw.mask & PSW_MASK_PSTATE) {
return 1; return 1;
@ -242,7 +242,7 @@ static inline int cpu_mmu_index (CPUState *env)
return 0; return 0;
} }
static inline void cpu_get_tb_cpu_state(CPUState* env, target_ulong *pc, static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
target_ulong *cs_base, int *flags) target_ulong *cs_base, int *flags)
{ {
*pc = env->psw.addr; *pc = env->psw.addr;
@ -275,7 +275,7 @@ CPUS390XState *cpu_s390x_init(const char *cpu_model);
void s390x_translate_init(void); void s390x_translate_init(void);
int cpu_s390x_exec(CPUS390XState *s); int cpu_s390x_exec(CPUS390XState *s);
void cpu_s390x_close(CPUS390XState *s); void cpu_s390x_close(CPUS390XState *s);
void do_interrupt (CPUState *env); void do_interrupt (CPUS390XState *env);
/* you can call this signal handler from your SIGBUS and SIGSEGV /* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero signal handlers to inform the virtual CPU of exceptions. non zero
@ -288,42 +288,42 @@ int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
int s390_virtio_hypercall(CPUState *env, uint64_t mem, uint64_t hypercall); int s390_virtio_hypercall(CPUS390XState *env, uint64_t mem, uint64_t hypercall);
#ifdef CONFIG_KVM #ifdef CONFIG_KVM
void kvm_s390_interrupt(CPUState *env, int type, uint32_t code); void kvm_s390_interrupt(CPUS390XState *env, int type, uint32_t code);
void kvm_s390_virtio_irq(CPUState *env, int config_change, uint64_t token); void kvm_s390_virtio_irq(CPUS390XState *env, int config_change, uint64_t token);
void kvm_s390_interrupt_internal(CPUState *env, int type, uint32_t parm, void kvm_s390_interrupt_internal(CPUS390XState *env, int type, uint32_t parm,
uint64_t parm64, int vm); uint64_t parm64, int vm);
#else #else
static inline void kvm_s390_interrupt(CPUState *env, int type, uint32_t code) static inline void kvm_s390_interrupt(CPUS390XState *env, int type, uint32_t code)
{ {
} }
static inline void kvm_s390_virtio_irq(CPUState *env, int config_change, static inline void kvm_s390_virtio_irq(CPUS390XState *env, int config_change,
uint64_t token) uint64_t token)
{ {
} }
static inline void kvm_s390_interrupt_internal(CPUState *env, int type, static inline void kvm_s390_interrupt_internal(CPUS390XState *env, int type,
uint32_t parm, uint64_t parm64, uint32_t parm, uint64_t parm64,
int vm) int vm)
{ {
} }
#endif #endif
CPUState *s390_cpu_addr2state(uint16_t cpu_addr); CPUS390XState *s390_cpu_addr2state(uint16_t cpu_addr);
void s390_add_running_cpu(CPUState *env); void s390_add_running_cpu(CPUS390XState *env);
unsigned s390_del_running_cpu(CPUState *env); unsigned s390_del_running_cpu(CPUS390XState *env);
/* from s390-virtio-bus */ /* from s390-virtio-bus */
extern const target_phys_addr_t virtio_size; extern const target_phys_addr_t virtio_size;
#else #else
static inline void s390_add_running_cpu(CPUState *env) static inline void s390_add_running_cpu(CPUS390XState *env)
{ {
} }
static inline unsigned s390_del_running_cpu(CPUState *env) static inline unsigned s390_del_running_cpu(CPUS390XState *env)
{ {
return 0; return 0;
} }
@ -944,11 +944,11 @@ static inline void ebcdic_put(uint8_t *p, const char *ascii, int len)
#define SIGP_STAT_INVALID_ORDER 0x00000002UL #define SIGP_STAT_INVALID_ORDER 0x00000002UL
#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
void load_psw(CPUState *env, uint64_t mask, uint64_t addr); void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
int mmu_translate(CPUState *env, target_ulong vaddr, int rw, uint64_t asc, int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
target_ulong *raddr, int *flags); target_ulong *raddr, int *flags);
int sclp_service_call(CPUState *env, uint32_t sccb, uint64_t code); int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code);
uint32_t calc_cc(CPUState *env, uint32_t cc_op, uint64_t src, uint64_t dst, uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
uint64_t vr); uint64_t vr);
#define TARGET_HAS_ICE 1 #define TARGET_HAS_ICE 1
@ -961,7 +961,7 @@ static inline uint64_t time2tod(uint64_t ns) {
return (ns << 9) / 125; return (ns << 9) / 125;
} }
static inline void cpu_inject_ext(CPUState *env, uint32_t code, uint32_t param, static inline void cpu_inject_ext(CPUS390XState *env, uint32_t code, uint32_t param,
uint64_t param64) uint64_t param64)
{ {
if (env->ext_index == MAX_EXT_QUEUE - 1) { if (env->ext_index == MAX_EXT_QUEUE - 1) {
@ -980,13 +980,13 @@ static inline void cpu_inject_ext(CPUState *env, uint32_t code, uint32_t param,
cpu_interrupt(env, CPU_INTERRUPT_HARD); cpu_interrupt(env, CPU_INTERRUPT_HARD);
} }
static inline bool cpu_has_work(CPUState *env) static inline bool cpu_has_work(CPUS390XState *env)
{ {
return (env->interrupt_request & CPU_INTERRUPT_HARD) && return (env->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->psw.mask & PSW_MASK_EXT); (env->psw.mask & PSW_MASK_EXT);
} }
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock* tb) static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
{ {
env->psw.addr = tb->pc; env->psw.addr = tb->pc;
} }

38
target-s390x/helper.c
View File

@ -53,7 +53,7 @@
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
static void s390x_tod_timer(void *opaque) static void s390x_tod_timer(void *opaque)
{ {
CPUState *env = opaque; CPUS390XState *env = opaque;
env->pending_int |= INTERRUPT_TOD; env->pending_int |= INTERRUPT_TOD;
cpu_interrupt(env, CPU_INTERRUPT_HARD); cpu_interrupt(env, CPU_INTERRUPT_HARD);
@ -61,7 +61,7 @@ static void s390x_tod_timer(void *opaque)
static void s390x_cpu_timer(void *opaque) static void s390x_cpu_timer(void *opaque)
{ {
CPUState *env = opaque; CPUS390XState *env = opaque;
env->pending_int |= INTERRUPT_CPUTIMER; env->pending_int |= INTERRUPT_CPUTIMER;
cpu_interrupt(env, CPU_INTERRUPT_HARD); cpu_interrupt(env, CPU_INTERRUPT_HARD);
@ -102,12 +102,12 @@ CPUS390XState *cpu_s390x_init(const char *cpu_model)
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
void do_interrupt (CPUState *env) void do_interrupt (CPUS390XState *env)
{ {
env->exception_index = -1; env->exception_index = -1;
} }
int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
int mmu_idx) int mmu_idx)
{ {
/* fprintf(stderr,"%s: address 0x%lx rw %d mmu_idx %d\n", /* fprintf(stderr,"%s: address 0x%lx rw %d mmu_idx %d\n",
@ -135,14 +135,14 @@ void cpu_state_reset(CPUS390XState *env)
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
/* Ensure to exit the TB after this call! */ /* Ensure to exit the TB after this call! */
static void trigger_pgm_exception(CPUState *env, uint32_t code, uint32_t ilc) static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilc)
{ {
env->exception_index = EXCP_PGM; env->exception_index = EXCP_PGM;
env->int_pgm_code = code; env->int_pgm_code = code;
env->int_pgm_ilc = ilc; env->int_pgm_ilc = ilc;
} }
static int trans_bits(CPUState *env, uint64_t mode) static int trans_bits(CPUS390XState *env, uint64_t mode)
{ {
int bits = 0; int bits = 0;
@ -164,7 +164,7 @@ static int trans_bits(CPUState *env, uint64_t mode)
return bits; return bits;
} }
static void trigger_prot_fault(CPUState *env, target_ulong vaddr, uint64_t mode) static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, uint64_t mode)
{ {
int ilc = ILC_LATER_INC_2; int ilc = ILC_LATER_INC_2;
int bits = trans_bits(env, mode) | 4; int bits = trans_bits(env, mode) | 4;
@ -175,7 +175,7 @@ static void trigger_prot_fault(CPUState *env, target_ulong vaddr, uint64_t mode)
trigger_pgm_exception(env, PGM_PROTECTION, ilc); trigger_pgm_exception(env, PGM_PROTECTION, ilc);
} }
static void trigger_page_fault(CPUState *env, target_ulong vaddr, uint32_t type, static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, uint32_t type,
uint64_t asc, int rw) uint64_t asc, int rw)
{ {
int ilc = ILC_LATER; int ilc = ILC_LATER;
@ -192,7 +192,7 @@ static void trigger_page_fault(CPUState *env, target_ulong vaddr, uint32_t type,
trigger_pgm_exception(env, type, ilc); trigger_pgm_exception(env, type, ilc);
} }
static int mmu_translate_asce(CPUState *env, target_ulong vaddr, uint64_t asc, static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t asc,
uint64_t asce, int level, target_ulong *raddr, uint64_t asce, int level, target_ulong *raddr,
int *flags, int rw) int *flags, int rw)
{ {
@ -274,7 +274,7 @@ static int mmu_translate_asce(CPUState *env, target_ulong vaddr, uint64_t asc,
return 0; return 0;
} }
static int mmu_translate_asc(CPUState *env, target_ulong vaddr, uint64_t asc, static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t asc,
target_ulong *raddr, int *flags, int rw) target_ulong *raddr, int *flags, int rw)
{ {
uint64_t asce = 0; uint64_t asce = 0;
@ -343,7 +343,7 @@ static int mmu_translate_asc(CPUState *env, target_ulong vaddr, uint64_t asc,
return r; return r;
} }
int mmu_translate(CPUState *env, target_ulong vaddr, int rw, uint64_t asc, int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
target_ulong *raddr, int *flags) target_ulong *raddr, int *flags)
{ {
int r = -1; int r = -1;
@ -404,7 +404,7 @@ out:
return r; return r;
} }
int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong _vaddr, int rw, int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong _vaddr, int rw,
int mmu_idx) int mmu_idx)
{ {
uint64_t asc = env->psw.mask & PSW_MASK_ASC; uint64_t asc = env->psw.mask & PSW_MASK_ASC;
@ -444,7 +444,7 @@ int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong _vaddr, int rw,
return 0; return 0;
} }
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong vaddr) target_phys_addr_t cpu_get_phys_page_debug(CPUS390XState *env, target_ulong vaddr)
{ {
target_ulong raddr; target_ulong raddr;
int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@ -462,7 +462,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong vaddr)
return raddr; return raddr;
} }
void load_psw(CPUState *env, uint64_t mask, uint64_t addr) void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
{ {
if (mask & PSW_MASK_WAIT) { if (mask & PSW_MASK_WAIT) {
if (!(mask & (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK))) { if (!(mask & (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK))) {
@ -481,7 +481,7 @@ void load_psw(CPUState *env, uint64_t mask, uint64_t addr)
env->cc_op = (mask >> 13) & 3; env->cc_op = (mask >> 13) & 3;
} }
static uint64_t get_psw_mask(CPUState *env) static uint64_t get_psw_mask(CPUS390XState *env)
{ {
uint64_t r = env->psw.mask; uint64_t r = env->psw.mask;
@ -494,7 +494,7 @@ static uint64_t get_psw_mask(CPUState *env)
return r; return r;
} }
static void do_svc_interrupt(CPUState *env) static void do_svc_interrupt(CPUS390XState *env)
{ {
uint64_t mask, addr; uint64_t mask, addr;
LowCore *lowcore; LowCore *lowcore;
@ -514,7 +514,7 @@ static void do_svc_interrupt(CPUState *env)
load_psw(env, mask, addr); load_psw(env, mask, addr);
} }
static void do_program_interrupt(CPUState *env) static void do_program_interrupt(CPUS390XState *env)
{ {
uint64_t mask, addr; uint64_t mask, addr;
LowCore *lowcore; LowCore *lowcore;
@ -557,7 +557,7 @@ static void do_program_interrupt(CPUState *env)
#define VIRTIO_SUBCODE_64 0x0D00 #define VIRTIO_SUBCODE_64 0x0D00
static void do_ext_interrupt(CPUState *env) static void do_ext_interrupt(CPUS390XState *env)
{ {
uint64_t mask, addr; uint64_t mask, addr;
LowCore *lowcore; LowCore *lowcore;
@ -597,7 +597,7 @@ static void do_ext_interrupt(CPUState *env)
load_psw(env, mask, addr); load_psw(env, mask, addr);
} }
void do_interrupt (CPUState *env) void do_interrupt (CPUS390XState *env)
{ {
qemu_log("%s: %d at pc=%" PRIx64 "\n", __FUNCTION__, env->exception_index, qemu_log("%s: %d at pc=%" PRIx64 "\n", __FUNCTION__, env->exception_index,
env->psw.addr); env->psw.addr);

56
target-s390x/kvm.c
View File

@ -72,7 +72,7 @@ int kvm_arch_init(KVMState *s)
return 0; return 0;
} }
int kvm_arch_init_vcpu(CPUState *env) int kvm_arch_init_vcpu(CPUS390XState *env)
{ {
int ret = 0; int ret = 0;
@ -83,12 +83,12 @@ int kvm_arch_init_vcpu(CPUState *env)
return ret; return ret;
} }
void kvm_arch_reset_vcpu(CPUState *env) void kvm_arch_reset_vcpu(CPUS390XState *env)
{ {
/* FIXME: add code to reset vcpu. */ /* FIXME: add code to reset vcpu. */
} }
int kvm_arch_put_registers(CPUState *env, int level) int kvm_arch_put_registers(CPUS390XState *env, int level)
{ {
struct kvm_regs regs; struct kvm_regs regs;
int ret; int ret;
@ -114,7 +114,7 @@ int kvm_arch_put_registers(CPUState *env, int level)
return ret; return ret;
} }
int kvm_arch_get_registers(CPUState *env) int kvm_arch_get_registers(CPUS390XState *env)
{ {
int ret; int ret;
struct kvm_regs regs; struct kvm_regs regs;
@ -135,7 +135,7 @@ int kvm_arch_get_registers(CPUState *env)
return 0; return 0;
} }
int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) int kvm_arch_insert_sw_breakpoint(CPUS390XState *env, struct kvm_sw_breakpoint *bp)
{ {
static const uint8_t diag_501[] = {0x83, 0x24, 0x05, 0x01}; static const uint8_t diag_501[] = {0x83, 0x24, 0x05, 0x01};
@ -146,7 +146,7 @@ int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
return 0; return 0;
} }
int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) int kvm_arch_remove_sw_breakpoint(CPUS390XState *env, struct kvm_sw_breakpoint *bp)
{ {
uint8_t t[4]; uint8_t t[4];
static const uint8_t diag_501[] = {0x83, 0x24, 0x05, 0x01}; static const uint8_t diag_501[] = {0x83, 0x24, 0x05, 0x01};
@ -162,20 +162,20 @@ int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
return 0; return 0;
} }
void kvm_arch_pre_run(CPUState *env, struct kvm_run *run) void kvm_arch_pre_run(CPUS390XState *env, struct kvm_run *run)
{ {
} }
void kvm_arch_post_run(CPUState *env, struct kvm_run *run) void kvm_arch_post_run(CPUS390XState *env, struct kvm_run *run)
{ {
} }
int kvm_arch_process_async_events(CPUState *env) int kvm_arch_process_async_events(CPUS390XState *env)
{ {
return env->halted; return env->halted;
} }
void kvm_s390_interrupt_internal(CPUState *env, int type, uint32_t parm, void kvm_s390_interrupt_internal(CPUS390XState *env, int type, uint32_t parm,
uint64_t parm64, int vm) uint64_t parm64, int vm)
{ {
struct kvm_s390_interrupt kvmint; struct kvm_s390_interrupt kvmint;
@ -201,23 +201,23 @@ void kvm_s390_interrupt_internal(CPUState *env, int type, uint32_t parm,
} }
} }
void kvm_s390_virtio_irq(CPUState *env, int config_change, uint64_t token) void kvm_s390_virtio_irq(CPUS390XState *env, int config_change, uint64_t token)
{ {
kvm_s390_interrupt_internal(env, KVM_S390_INT_VIRTIO, config_change, kvm_s390_interrupt_internal(env, KVM_S390_INT_VIRTIO, config_change,
token, 1); token, 1);
} }
void kvm_s390_interrupt(CPUState *env, int type, uint32_t code) void kvm_s390_interrupt(CPUS390XState *env, int type, uint32_t code)
{ {
kvm_s390_interrupt_internal(env, type, code, 0, 0); kvm_s390_interrupt_internal(env, type, code, 0, 0);
} }
static void enter_pgmcheck(CPUState *env, uint16_t code) static void enter_pgmcheck(CPUS390XState *env, uint16_t code)
{ {
kvm_s390_interrupt(env, KVM_S390_PROGRAM_INT, code); kvm_s390_interrupt(env, KVM_S390_PROGRAM_INT, code);
} }
static inline void setcc(CPUState *env, uint64_t cc) static inline void setcc(CPUS390XState *env, uint64_t cc)
{ {
env->kvm_run->psw_mask &= ~(3ull << 44); env->kvm_run->psw_mask &= ~(3ull << 44);
env->kvm_run->psw_mask |= (cc & 3) << 44; env->kvm_run->psw_mask |= (cc & 3) << 44;
@ -226,7 +226,7 @@ static inline void setcc(CPUState *env, uint64_t cc)
env->psw.mask |= (cc & 3) << 44; env->psw.mask |= (cc & 3) << 44;
} }
static int kvm_sclp_service_call(CPUState *env, struct kvm_run *run, static int kvm_sclp_service_call(CPUS390XState *env, struct kvm_run *run,
uint16_t ipbh0) uint16_t ipbh0)
{ {
uint32_t sccb; uint32_t sccb;
@ -245,7 +245,7 @@ static int kvm_sclp_service_call(CPUState *env, struct kvm_run *run,
return 0; return 0;
} }
static int handle_priv(CPUState *env, struct kvm_run *run, uint8_t ipa1) static int handle_priv(CPUS390XState *env, struct kvm_run *run, uint8_t ipa1)
{ {
int r = 0; int r = 0;
uint16_t ipbh0 = (run->s390_sieic.ipb & 0xffff0000) >> 16; uint16_t ipbh0 = (run->s390_sieic.ipb & 0xffff0000) >> 16;
@ -264,7 +264,7 @@ static int handle_priv(CPUState *env, struct kvm_run *run, uint8_t ipa1)
return r; return r;
} }
static int handle_hypercall(CPUState *env, struct kvm_run *run) static int handle_hypercall(CPUS390XState *env, struct kvm_run *run)
{ {
cpu_synchronize_state(env); cpu_synchronize_state(env);
env->regs[2] = s390_virtio_hypercall(env, env->regs[2], env->regs[1]); env->regs[2] = s390_virtio_hypercall(env, env->regs[2], env->regs[1]);
@ -272,7 +272,7 @@ static int handle_hypercall(CPUState *env, struct kvm_run *run)
return 0; return 0;
} }
static int handle_diag(CPUState *env, struct kvm_run *run, int ipb_code) static int handle_diag(CPUS390XState *env, struct kvm_run *run, int ipb_code)
{ {
int r = 0; int r = 0;
@ -292,7 +292,7 @@ static int handle_diag(CPUState *env, struct kvm_run *run, int ipb_code)
return r; return r;
} }
static int s390_cpu_restart(CPUState *env) static int s390_cpu_restart(CPUS390XState *env)
{ {
kvm_s390_interrupt(env, KVM_S390_RESTART, 0); kvm_s390_interrupt(env, KVM_S390_RESTART, 0);
s390_add_running_cpu(env); s390_add_running_cpu(env);
@ -301,14 +301,14 @@ static int s390_cpu_restart(CPUState *env)
return 0; return 0;
} }
static int s390_store_status(CPUState *env, uint32_t parameter) static int s390_store_status(CPUS390XState *env, uint32_t parameter)
{ {
/* XXX */ /* XXX */
fprintf(stderr, "XXX SIGP store status\n"); fprintf(stderr, "XXX SIGP store status\n");
return -1; return -1;
} }
static int s390_cpu_initial_reset(CPUState *env) static int s390_cpu_initial_reset(CPUS390XState *env)
{ {
int i; int i;
@ -326,14 +326,14 @@ static int s390_cpu_initial_reset(CPUState *env)
return 0; return 0;
} }
static int handle_sigp(CPUState *env, struct kvm_run *run, uint8_t ipa1) static int handle_sigp(CPUS390XState *env, struct kvm_run *run, uint8_t ipa1)
{ {
uint8_t order_code; uint8_t order_code;
uint32_t parameter; uint32_t parameter;
uint16_t cpu_addr; uint16_t cpu_addr;
uint8_t t; uint8_t t;
int r = -1; int r = -1;
CPUState *target_env; CPUS390XState *target_env;
cpu_synchronize_state(env); cpu_synchronize_state(env);
@ -381,7 +381,7 @@ out:
return 0; return 0;
} }
static int handle_instruction(CPUState *env, struct kvm_run *run) static int handle_instruction(CPUS390XState *env, struct kvm_run *run)
{ {
unsigned int ipa0 = (run->s390_sieic.ipa & 0xff00); unsigned int ipa0 = (run->s390_sieic.ipa & 0xff00);
uint8_t ipa1 = run->s390_sieic.ipa & 0x00ff; uint8_t ipa1 = run->s390_sieic.ipa & 0x00ff;
@ -407,7 +407,7 @@ static int handle_instruction(CPUState *env, struct kvm_run *run)
return 0; return 0;
} }
static int handle_intercept(CPUState *env) static int handle_intercept(CPUS390XState *env)
{ {
struct kvm_run *run = env->kvm_run; struct kvm_run *run = env->kvm_run;
int icpt_code = run->s390_sieic.icptcode; int icpt_code = run->s390_sieic.icptcode;
@ -443,7 +443,7 @@ static int handle_intercept(CPUState *env)
return r; return r;
} }
int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) int kvm_arch_handle_exit(CPUS390XState *env, struct kvm_run *run)
{ {
int ret = 0; int ret = 0;
@ -466,12 +466,12 @@ int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
return ret; return ret;
} }
bool kvm_arch_stop_on_emulation_error(CPUState *env) bool kvm_arch_stop_on_emulation_error(CPUS390XState *env)
{ {
return true; return true;
} }
int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr) int kvm_arch_on_sigbus_vcpu(CPUS390XState *env, int code, void *addr)
{ {
return 1; return 1;
} }

70
target-s390x/op_helper.c
View File

@ -56,11 +56,11 @@
NULL, it means that the function was called in C code (i.e. not NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */ from generated code or from helper.c) */
/* XXX: fix it to restore all registers */ /* XXX: fix it to restore all registers */
void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx, void tlb_fill(CPUS390XState *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr) void *retaddr)
{ {
TranslationBlock *tb; TranslationBlock *tb;
CPUState *saved_env; CPUS390XState *saved_env;
unsigned long pc; unsigned long pc;
int ret; int ret;
@ -101,7 +101,7 @@ void HELPER(exception)(uint32_t excp)
} }
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
static void mvc_fast_memset(CPUState *env, uint32_t l, uint64_t dest, static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest,
uint8_t byte) uint8_t byte)
{ {
target_phys_addr_t dest_phys; target_phys_addr_t dest_phys;
@ -123,7 +123,7 @@ static void mvc_fast_memset(CPUState *env, uint32_t l, uint64_t dest,
cpu_physical_memory_unmap(dest_p, 1, len, len); cpu_physical_memory_unmap(dest_p, 1, len, len);
} }
static void mvc_fast_memmove(CPUState *env, uint32_t l, uint64_t dest, static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest,
uint64_t src) uint64_t src)
{ {
target_phys_addr_t dest_phys; target_phys_addr_t dest_phys;
@ -1790,7 +1790,7 @@ void HELPER(cksm)(uint32_t r1, uint32_t r2)
((uint32_t)cksm + (cksm >> 32)); ((uint32_t)cksm + (cksm >> 32));
} }
static inline uint32_t cc_calc_ltgt_32(CPUState *env, int32_t src, static inline uint32_t cc_calc_ltgt_32(CPUS390XState *env, int32_t src,
int32_t dst) int32_t dst)
{ {
if (src == dst) { if (src == dst) {
@ -1802,12 +1802,12 @@ static inline uint32_t cc_calc_ltgt_32(CPUState *env, int32_t src,
} }
} }
static inline uint32_t cc_calc_ltgt0_32(CPUState *env, int32_t dst) static inline uint32_t cc_calc_ltgt0_32(CPUS390XState *env, int32_t dst)
{ {
return cc_calc_ltgt_32(env, dst, 0); return cc_calc_ltgt_32(env, dst, 0);
} }
static inline uint32_t cc_calc_ltgt_64(CPUState *env, int64_t src, static inline uint32_t cc_calc_ltgt_64(CPUS390XState *env, int64_t src,
int64_t dst) int64_t dst)
{ {
if (src == dst) { if (src == dst) {
@ -1819,12 +1819,12 @@ static inline uint32_t cc_calc_ltgt_64(CPUState *env, int64_t src,
} }
} }
static inline uint32_t cc_calc_ltgt0_64(CPUState *env, int64_t dst) static inline uint32_t cc_calc_ltgt0_64(CPUS390XState *env, int64_t dst)
{ {
return cc_calc_ltgt_64(env, dst, 0); return cc_calc_ltgt_64(env, dst, 0);
} }
static inline uint32_t cc_calc_ltugtu_32(CPUState *env, uint32_t src, static inline uint32_t cc_calc_ltugtu_32(CPUS390XState *env, uint32_t src,
uint32_t dst) uint32_t dst)
{ {
if (src == dst) { if (src == dst) {
@ -1836,7 +1836,7 @@ static inline uint32_t cc_calc_ltugtu_32(CPUState *env, uint32_t src,
} }
} }
static inline uint32_t cc_calc_ltugtu_64(CPUState *env, uint64_t src, static inline uint32_t cc_calc_ltugtu_64(CPUS390XState *env, uint64_t src,
uint64_t dst) uint64_t dst)
{ {
if (src == dst) { if (src == dst) {
@ -1848,7 +1848,7 @@ static inline uint32_t cc_calc_ltugtu_64(CPUState *env, uint64_t src,
} }
} }
static inline uint32_t cc_calc_tm_32(CPUState *env, uint32_t val, uint32_t mask) static inline uint32_t cc_calc_tm_32(CPUS390XState *env, uint32_t val, uint32_t mask)
{ {
HELPER_LOG("%s: val 0x%x mask 0x%x\n", __FUNCTION__, val, mask); HELPER_LOG("%s: val 0x%x mask 0x%x\n", __FUNCTION__, val, mask);
uint16_t r = val & mask; uint16_t r = val & mask;
@ -1862,7 +1862,7 @@ static inline uint32_t cc_calc_tm_32(CPUState *env, uint32_t val, uint32_t mask)
} }
/* set condition code for test under mask */ /* set condition code for test under mask */
static inline uint32_t cc_calc_tm_64(CPUState *env, uint64_t val, uint32_t mask) static inline uint32_t cc_calc_tm_64(CPUS390XState *env, uint64_t val, uint32_t mask)
{ {
uint16_t r = val & mask; uint16_t r = val & mask;
HELPER_LOG("%s: val 0x%lx mask 0x%x r 0x%x\n", __FUNCTION__, val, mask, r); HELPER_LOG("%s: val 0x%lx mask 0x%x r 0x%x\n", __FUNCTION__, val, mask, r);
@ -1883,12 +1883,12 @@ static inline uint32_t cc_calc_tm_64(CPUState *env, uint64_t val, uint32_t mask)
} }
} }
static inline uint32_t cc_calc_nz(CPUState *env, uint64_t dst) static inline uint32_t cc_calc_nz(CPUS390XState *env, uint64_t dst)
{ {
return !!dst; return !!dst;
} }
static inline uint32_t cc_calc_add_64(CPUState *env, int64_t a1, int64_t a2, static inline uint32_t cc_calc_add_64(CPUS390XState *env, int64_t a1, int64_t a2,
int64_t ar) int64_t ar)
{ {
if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) { if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) {
@ -1904,7 +1904,7 @@ static inline uint32_t cc_calc_add_64(CPUState *env, int64_t a1, int64_t a2,
} }
} }
static inline uint32_t cc_calc_addu_64(CPUState *env, uint64_t a1, uint64_t a2, static inline uint32_t cc_calc_addu_64(CPUS390XState *env, uint64_t a1, uint64_t a2,
uint64_t ar) uint64_t ar)
{ {
if (ar == 0) { if (ar == 0) {
@ -1922,7 +1922,7 @@ static inline uint32_t cc_calc_addu_64(CPUState *env, uint64_t a1, uint64_t a2,
} }
} }
static inline uint32_t cc_calc_sub_64(CPUState *env, int64_t a1, int64_t a2, static inline uint32_t cc_calc_sub_64(CPUS390XState *env, int64_t a1, int64_t a2,
int64_t ar) int64_t ar)
{ {
if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) { if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) {
@ -1938,7 +1938,7 @@ static inline uint32_t cc_calc_sub_64(CPUState *env, int64_t a1, int64_t a2,
} }
} }
static inline uint32_t cc_calc_subu_64(CPUState *env, uint64_t a1, uint64_t a2, static inline uint32_t cc_calc_subu_64(CPUS390XState *env, uint64_t a1, uint64_t a2,
uint64_t ar) uint64_t ar)
{ {
if (ar == 0) { if (ar == 0) {
@ -1952,7 +1952,7 @@ static inline uint32_t cc_calc_subu_64(CPUState *env, uint64_t a1, uint64_t a2,
} }
} }
static inline uint32_t cc_calc_abs_64(CPUState *env, int64_t dst) static inline uint32_t cc_calc_abs_64(CPUS390XState *env, int64_t dst)
{ {
if ((uint64_t)dst == 0x8000000000000000ULL) { if ((uint64_t)dst == 0x8000000000000000ULL) {
return 3; return 3;
@ -1963,12 +1963,12 @@ static inline uint32_t cc_calc_abs_64(CPUState *env, int64_t dst)
} }
} }
static inline uint32_t cc_calc_nabs_64(CPUState *env, int64_t dst) static inline uint32_t cc_calc_nabs_64(CPUS390XState *env, int64_t dst)
{ {
return !!dst; return !!dst;
} }
static inline uint32_t cc_calc_comp_64(CPUState *env, int64_t dst) static inline uint32_t cc_calc_comp_64(CPUS390XState *env, int64_t dst)
{ {
if ((uint64_t)dst == 0x8000000000000000ULL) { if ((uint64_t)dst == 0x8000000000000000ULL) {
return 3; return 3;
@ -1982,7 +1982,7 @@ static inline uint32_t cc_calc_comp_64(CPUState *env, int64_t dst)
} }
static inline uint32_t cc_calc_add_32(CPUState *env, int32_t a1, int32_t a2, static inline uint32_t cc_calc_add_32(CPUS390XState *env, int32_t a1, int32_t a2,
int32_t ar) int32_t ar)
{ {
if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) { if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) {
@ -1998,7 +1998,7 @@ static inline uint32_t cc_calc_add_32(CPUState *env, int32_t a1, int32_t a2,
} }
} }
static inline uint32_t cc_calc_addu_32(CPUState *env, uint32_t a1, uint32_t a2, static inline uint32_t cc_calc_addu_32(CPUS390XState *env, uint32_t a1, uint32_t a2,
uint32_t ar) uint32_t ar)
{ {
if (ar == 0) { if (ar == 0) {
@ -2016,7 +2016,7 @@ static inline uint32_t cc_calc_addu_32(CPUState *env, uint32_t a1, uint32_t a2,
} }
} }
static inline uint32_t cc_calc_sub_32(CPUState *env, int32_t a1, int32_t a2, static inline uint32_t cc_calc_sub_32(CPUS390XState *env, int32_t a1, int32_t a2,
int32_t ar) int32_t ar)
{ {
if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) { if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) {
@ -2032,7 +2032,7 @@ static inline uint32_t cc_calc_sub_32(CPUState *env, int32_t a1, int32_t a2,
} }
} }
static inline uint32_t cc_calc_subu_32(CPUState *env, uint32_t a1, uint32_t a2, static inline uint32_t cc_calc_subu_32(CPUS390XState *env, uint32_t a1, uint32_t a2,
uint32_t ar) uint32_t ar)
{ {
if (ar == 0) { if (ar == 0) {
@ -2046,7 +2046,7 @@ static inline uint32_t cc_calc_subu_32(CPUState *env, uint32_t a1, uint32_t a2,
} }
} }
static inline uint32_t cc_calc_abs_32(CPUState *env, int32_t dst) static inline uint32_t cc_calc_abs_32(CPUS390XState *env, int32_t dst)
{ {
if ((uint32_t)dst == 0x80000000UL) { if ((uint32_t)dst == 0x80000000UL) {
return 3; return 3;
@ -2057,12 +2057,12 @@ static inline uint32_t cc_calc_abs_32(CPUState *env, int32_t dst)
} }
} }
static inline uint32_t cc_calc_nabs_32(CPUState *env, int32_t dst) static inline uint32_t cc_calc_nabs_32(CPUS390XState *env, int32_t dst)
{ {
return !!dst; return !!dst;
} }
static inline uint32_t cc_calc_comp_32(CPUState *env, int32_t dst) static inline uint32_t cc_calc_comp_32(CPUS390XState *env, int32_t dst)
{ {
if ((uint32_t)dst == 0x80000000UL) { if ((uint32_t)dst == 0x80000000UL) {
return 3; return 3;
@ -2076,7 +2076,7 @@ static inline uint32_t cc_calc_comp_32(CPUState *env, int32_t dst)
} }
/* calculate condition code for insert character under mask insn */ /* calculate condition code for insert character under mask insn */
static inline uint32_t cc_calc_icm_32(CPUState *env, uint32_t mask, uint32_t val) static inline uint32_t cc_calc_icm_32(CPUS390XState *env, uint32_t mask, uint32_t val)
{ {
HELPER_LOG("%s: mask 0x%x val %d\n", __FUNCTION__, mask, val); HELPER_LOG("%s: mask 0x%x val %d\n", __FUNCTION__, mask, val);
uint32_t cc; uint32_t cc;
@ -2107,7 +2107,7 @@ static inline uint32_t cc_calc_icm_32(CPUState *env, uint32_t mask, uint32_t val
return cc; return cc;
} }
static inline uint32_t cc_calc_slag(CPUState *env, uint64_t src, uint64_t shift) static inline uint32_t cc_calc_slag(CPUS390XState *env, uint64_t src, uint64_t shift)
{ {
uint64_t mask = ((1ULL << shift) - 1ULL) << (64 - shift); uint64_t mask = ((1ULL << shift) - 1ULL) << (64 - shift);
uint64_t match, r; uint64_t match, r;
@ -2136,7 +2136,7 @@ static inline uint32_t cc_calc_slag(CPUState *env, uint64_t src, uint64_t shift)
} }
static inline uint32_t do_calc_cc(CPUState *env, uint32_t cc_op, uint64_t src, static inline uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src,
uint64_t dst, uint64_t vr) uint64_t dst, uint64_t vr)
{ {
uint32_t r = 0; uint32_t r = 0;
@ -2249,7 +2249,7 @@ static inline uint32_t do_calc_cc(CPUState *env, uint32_t cc_op, uint64_t src,
return r; return r;
} }
uint32_t calc_cc(CPUState *env, uint32_t cc_op, uint64_t src, uint64_t dst, uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
uint64_t vr) uint64_t vr)
{ {
return do_calc_cc(env, cc_op, src, dst, vr); return do_calc_cc(env, cc_op, src, dst, vr);
@ -2346,7 +2346,7 @@ void HELPER(load_psw)(uint64_t mask, uint64_t addr)
cpu_loop_exit(env); cpu_loop_exit(env);
} }
static void program_interrupt(CPUState *env, uint32_t code, int ilc) static void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
{ {
qemu_log("program interrupt at %#" PRIx64 "\n", env->psw.addr); qemu_log("program interrupt at %#" PRIx64 "\n", env->psw.addr);
@ -2362,13 +2362,13 @@ static void program_interrupt(CPUState *env, uint32_t code, int ilc)
} }
} }
static void ext_interrupt(CPUState *env, int type, uint32_t param, static void ext_interrupt(CPUS390XState *env, int type, uint32_t param,
uint64_t param64) uint64_t param64)
{ {
cpu_inject_ext(env, type, param, param64); cpu_inject_ext(env, type, param, param64);
} }
int sclp_service_call(CPUState *env, uint32_t sccb, uint64_t code) int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code)
{ {
int r = 0; int r = 0;
int shift = 0; int shift = 0;
@ -2481,7 +2481,7 @@ uint32_t HELPER(sck)(uint64_t a1)
return 0; return 0;
} }
static inline uint64_t clock_value(CPUState *env) static inline uint64_t clock_value(CPUS390XState *env)
{ {
uint64_t time; uint64_t time;

56
target-s390x/translate.c
View File

@ -74,7 +74,7 @@ static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
return pc; return pc;
} }
void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf, void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
int flags) int flags)
{ {
int i; int i;
@ -148,25 +148,25 @@ void s390x_translate_init(void)
char *p; char *p;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
psw_addr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, psw.addr), psw_addr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, psw.addr),
"psw_addr"); "psw_addr");
psw_mask = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, psw.mask), psw_mask = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, psw.mask),
"psw_mask"); "psw_mask");
cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op), cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
"cc_op"); "cc_op");
cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_src), cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
"cc_src"); "cc_src");
cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_dst), cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
"cc_dst"); "cc_dst");
cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_vr), cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
"cc_vr"); "cc_vr");
p = cpu_reg_names; p = cpu_reg_names;
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
snprintf(p, cpu_reg_names_size, "r%d", i); snprintf(p, cpu_reg_names_size, "r%d", i);
regs[i] = tcg_global_mem_new(TCG_AREG0, regs[i] = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, regs[i]), p); offsetof(CPUS390XState, regs[i]), p);
p += (i < 10) ? 3 : 4; p += (i < 10) ? 3 : 4;
cpu_reg_names_size -= (i < 10) ? 3 : 4; cpu_reg_names_size -= (i < 10) ? 3 : 4;
} }
@ -182,14 +182,14 @@ static inline TCGv_i64 load_reg(int reg)
static inline TCGv_i64 load_freg(int reg) static inline TCGv_i64 load_freg(int reg)
{ {
TCGv_i64 r = tcg_temp_new_i64(); TCGv_i64 r = tcg_temp_new_i64();
tcg_gen_ld_i64(r, cpu_env, offsetof(CPUState, fregs[reg].d)); tcg_gen_ld_i64(r, cpu_env, offsetof(CPUS390XState, fregs[reg].d));
return r; return r;
} }
static inline TCGv_i32 load_freg32(int reg) static inline TCGv_i32 load_freg32(int reg)
{ {
TCGv_i32 r = tcg_temp_new_i32(); TCGv_i32 r = tcg_temp_new_i32();
tcg_gen_ld_i32(r, cpu_env, offsetof(CPUState, fregs[reg].l.upper)); tcg_gen_ld_i32(r, cpu_env, offsetof(CPUS390XState, fregs[reg].l.upper));
return r; return r;
} }
@ -214,7 +214,7 @@ static inline void store_reg(int reg, TCGv_i64 v)
static inline void store_freg(int reg, TCGv_i64 v) static inline void store_freg(int reg, TCGv_i64 v)
{ {
tcg_gen_st_i64(v, cpu_env, offsetof(CPUState, fregs[reg].d)); tcg_gen_st_i64(v, cpu_env, offsetof(CPUS390XState, fregs[reg].d));
} }
static inline void store_reg32(int reg, TCGv_i32 v) static inline void store_reg32(int reg, TCGv_i32 v)
@ -257,7 +257,7 @@ static inline void store_reg8(int reg, TCGv_i64 v)
static inline void store_freg32(int reg, TCGv_i32 v) static inline void store_freg32(int reg, TCGv_i32 v)
{ {
tcg_gen_st_i32(v, cpu_env, offsetof(CPUState, fregs[reg].l.upper)); tcg_gen_st_i32(v, cpu_env, offsetof(CPUS390XState, fregs[reg].l.upper));
} }
static inline void update_psw_addr(DisasContext *s) static inline void update_psw_addr(DisasContext *s)
@ -361,11 +361,11 @@ static void gen_program_exception(DisasContext *s, int ilc, int code)
/* remember what pgm exeption this was */ /* remember what pgm exeption this was */
tmp = tcg_const_i32(code); tmp = tcg_const_i32(code);
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, int_pgm_code)); tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
tcg_temp_free_i32(tmp); tcg_temp_free_i32(tmp);
tmp = tcg_const_i32(ilc); tmp = tcg_const_i32(ilc);
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, int_pgm_ilc)); tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilc));
tcg_temp_free_i32(tmp); tcg_temp_free_i32(tmp);
/* advance past instruction */ /* advance past instruction */
@ -2647,12 +2647,12 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
break; break;
case 0x4e: /* SAR R1,R2 [RRE] */ case 0x4e: /* SAR R1,R2 [RRE] */
tmp32_1 = load_reg32(r2); tmp32_1 = load_reg32(r2);
tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, aregs[r1])); tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, aregs[r1]));
tcg_temp_free_i32(tmp32_1); tcg_temp_free_i32(tmp32_1);
break; break;
case 0x4f: /* EAR R1,R2 [RRE] */ case 0x4f: /* EAR R1,R2 [RRE] */
tmp32_1 = tcg_temp_new_i32(); tmp32_1 = tcg_temp_new_i32();
tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, aregs[r2])); tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, aregs[r2]));
store_reg32(r1, tmp32_1); store_reg32(r1, tmp32_1);
tcg_temp_free_i32(tmp32_1); tcg_temp_free_i32(tmp32_1);
break; break;
@ -2807,7 +2807,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
decode_rs(s, insn, &r1, &r3, &b2, &d2); decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2); tmp = get_address(s, 0, b2, d2);
tmp2 = tcg_temp_new_i64(); tmp2 = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp2, cpu_env, offsetof(CPUState, psa)); tcg_gen_ld_i64(tmp2, cpu_env, offsetof(CPUS390XState, psa));
tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s)); tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
tcg_temp_free_i64(tmp); tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2); tcg_temp_free_i64(tmp2);
@ -2819,7 +2819,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
tmp = get_address(s, 0, b2, d2); tmp = get_address(s, 0, b2, d2);
tmp2 = tcg_temp_new_i64(); tmp2 = tcg_temp_new_i64();
tmp32_1 = tcg_temp_new_i32(); tmp32_1 = tcg_temp_new_i32();
tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, cpu_num)); tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, cpu_num));
tcg_gen_extu_i32_i64(tmp2, tmp32_1); tcg_gen_extu_i32_i64(tmp2, tmp32_1);
tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s)); tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
tcg_temp_free_i64(tmp); tcg_temp_free_i64(tmp);
@ -2948,7 +2948,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
tmp32_1 = tcg_temp_new_i32(); tmp32_1 = tcg_temp_new_i32();
tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s)); tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
tcg_gen_trunc_i64_i32(tmp32_1, tmp2); tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc)); tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
tcg_temp_free_i64(tmp); tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2); tcg_temp_free_i64(tmp2);
tcg_temp_free_i32(tmp32_1); tcg_temp_free_i32(tmp32_1);
@ -3158,12 +3158,12 @@ static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)
break; break;
case 0x84: /* SFPC R1 [RRE] */ case 0x84: /* SFPC R1 [RRE] */
tmp32_1 = load_reg32(r1); tmp32_1 = load_reg32(r1);
tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc)); tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
tcg_temp_free_i32(tmp32_1); tcg_temp_free_i32(tmp32_1);
break; break;
case 0x8c: /* EFPC R1 [RRE] */ case 0x8c: /* EFPC R1 [RRE] */
tmp32_1 = tcg_temp_new_i32(); tmp32_1 = tcg_temp_new_i32();
tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc)); tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
store_reg32(r1, tmp32_1); store_reg32(r1, tmp32_1);
tcg_temp_free_i32(tmp32_1); tcg_temp_free_i32(tmp32_1);
break; break;
@ -3929,8 +3929,8 @@ static void disas_s390_insn(DisasContext *s)
tmp32_1 = tcg_const_i32(i); tmp32_1 = tcg_const_i32(i);
tmp32_2 = tcg_const_i32(ilc * 2); tmp32_2 = tcg_const_i32(ilc * 2);
tmp32_3 = tcg_const_i32(EXCP_SVC); tmp32_3 = tcg_const_i32(EXCP_SVC);
tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, int_svc_code)); tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, int_svc_code));
tcg_gen_st_i32(tmp32_2, cpu_env, offsetof(CPUState, int_svc_ilc)); tcg_gen_st_i32(tmp32_2, cpu_env, offsetof(CPUS390XState, int_svc_ilc));
gen_helper_exception(tmp32_3); gen_helper_exception(tmp32_3);
s->is_jmp = DISAS_EXCP; s->is_jmp = DISAS_EXCP;
tcg_temp_free_i32(tmp32_1); tcg_temp_free_i32(tmp32_1);
@ -4810,7 +4810,7 @@ static void disas_s390_insn(DisasContext *s)
tmp32_1 = tcg_temp_new_i32(); tmp32_1 = tcg_temp_new_i32();
tmp = tcg_temp_new_i64(); tmp = tcg_temp_new_i64();
tmp2 = get_address(s, 0, b2, d2); tmp2 = get_address(s, 0, b2, d2);
tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc)); tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
tcg_gen_extu_i32_i64(tmp, tmp32_1); tcg_gen_extu_i32_i64(tmp, tmp32_1);
tcg_gen_qemu_st32(tmp, tmp2, get_mem_index(s)); tcg_gen_qemu_st32(tmp, tmp2, get_mem_index(s));
tcg_temp_free_i32(tmp32_1); tcg_temp_free_i32(tmp32_1);
@ -5107,7 +5107,7 @@ static void disas_s390_insn(DisasContext *s)
s->pc += (ilc * 2); s->pc += (ilc * 2);
} }
static inline void gen_intermediate_code_internal(CPUState *env, static inline void gen_intermediate_code_internal(CPUS390XState *env,
TranslationBlock *tb, TranslationBlock *tb,
int search_pc) int search_pc)
{ {
@ -5223,17 +5223,17 @@ static inline void gen_intermediate_code_internal(CPUState *env,
#endif #endif
} }
void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
{ {
gen_intermediate_code_internal(env, tb, 0); gen_intermediate_code_internal(env, tb, 0);
} }
void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
{ {
gen_intermediate_code_internal(env, tb, 1); gen_intermediate_code_internal(env, tb, 1);
} }
void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos) void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
{ {
int cc_op; int cc_op;
env->psw.addr = gen_opc_pc[pc_pos]; env->psw.addr = gen_opc_pc[pc_pos];