x86 queue, 2018-06-11
* Support for CPUID[0x8000001D] (AMD Cache Topology Information) * pc bug fix: Remove PC_COMPAT_2_12 from 3.0 machine-types -----BEGIN PGP SIGNATURE----- iQIcBAABCAAGBQJbHq/oAAoJECgHk2+YTcWmWUgP/RmWEa6DMScwnlt6mejqrd6+ H+s5haYE2vNzb91FrL/65d1FmOkkvkYcSdkuOkuJjIvkPdGm95pcIR1mpkw/hiUt fsxH1zPWVNufF6dC6+REefQGyAK9ZhE0zLQBJNXgMaum5Ggw5yTsbSMJnLTpAbyZ /s0Gy9FjJgFuM++HSRV+G8e4TPGDOelBH2s+yVFevd7Z/uFcFwbJLIEhsuo8ctvx wIJNvNQCiEUv3C7Krexw67LDXXnH6ijnmpJVP1WRD3e/ESlo8OQVwUTDvlB5Kc7/ UNOhZju/I6Rn8lL1QG1pqY5gTICVuBloY37ek4o27pKUMUZ9CVVg68xePc4gQsjX BcMwsTyVI86fd7SxLmt+opR7ng2lT3CrG8QMPjQpAg0y8wn20jUeGGBm4CgmggrK RGcOfT0RtAGfB381rbseDlPMs89GP7Pxv9FtRUU72ppRPuV95mMEsUoh681NM2kh GUu5kUzy78reA+FitGRYoHzKrYwZsuY40JEQSvK9Z3ok2bsOMYf2kCpL+Ef6HN4i UfgsXNPXH8VLegZELf9L6YcH5981QhL4csJBCzJLHpG0lvpp12hvVL2EmDoSVZOK NZruj/rhoeECevq0pLy6JXszECWCM3+D9BKGJkyRZ4DBvnIbU/1yrNhB2rBTNPa4 UXYrcKcCm6xcN+zFSeFs =TunR -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' into staging x86 queue, 2018-06-11 * Support for CPUID[0x8000001D] (AMD Cache Topology Information) * pc bug fix: Remove PC_COMPAT_2_12 from 3.0 machine-types # gpg: Signature made Mon 11 Jun 2018 18:22:48 BST # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-next-pull-request: pc: Remove PC_COMPAT_2_12 from 3.0 machine-types i386: Populate AMD Processor Cache Information for cpuid 0x8000001D i386: Clean up cache CPUID code Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
a48f7644f8
@ -430,7 +430,6 @@ static void pc_i440fx_3_0_machine_options(MachineClass *m)
|
||||
pc_i440fx_machine_options(m);
|
||||
m->alias = "pc";
|
||||
m->is_default = 1;
|
||||
SET_MACHINE_COMPAT(m, PC_COMPAT_2_12);
|
||||
}
|
||||
|
||||
DEFINE_I440FX_MACHINE(v3_0, "pc-i440fx-3.0", NULL,
|
||||
|
||||
@ -312,7 +312,6 @@ static void pc_q35_3_0_machine_options(MachineClass *m)
|
||||
{
|
||||
pc_q35_machine_options(m);
|
||||
m->alias = "q35";
|
||||
SET_MACHINE_COMPAT(m, PC_COMPAT_2_12);
|
||||
}
|
||||
|
||||
DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL,
|
||||
|
||||
@ -334,6 +334,99 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
|
||||
* Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
|
||||
* Define the constants to build the cpu topology. Right now, TOPOEXT
|
||||
* feature is enabled only on EPYC. So, these constants are based on
|
||||
* EPYC supported configurations. We may need to handle the cases if
|
||||
* these values change in future.
|
||||
*/
|
||||
/* Maximum core complexes in a node */
|
||||
#define MAX_CCX 2
|
||||
/* Maximum cores in a core complex */
|
||||
#define MAX_CORES_IN_CCX 4
|
||||
/* Maximum cores in a node */
|
||||
#define MAX_CORES_IN_NODE 8
|
||||
/* Maximum nodes in a socket */
|
||||
#define MAX_NODES_PER_SOCKET 4
|
||||
|
||||
/*
|
||||
* Figure out the number of nodes required to build this config.
|
||||
* Max cores in a node is 8
|
||||
*/
|
||||
static int nodes_in_socket(int nr_cores)
|
||||
{
|
||||
int nodes;
|
||||
|
||||
nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
|
||||
|
||||
/* Hardware does not support config with 3 nodes, return 4 in that case */
|
||||
return (nodes == 3) ? 4 : nodes;
|
||||
}
|
||||
|
||||
/*
|
||||
* Decide the number of cores in a core complex with the given nr_cores using
|
||||
* following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
|
||||
* MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
|
||||
* L3 cache is shared across all cores in a core complex. So, this will also
|
||||
* tell us how many cores are sharing the L3 cache.
|
||||
*/
|
||||
static int cores_in_core_complex(int nr_cores)
|
||||
{
|
||||
int nodes;
|
||||
|
||||
/* Check if we can fit all the cores in one core complex */
|
||||
if (nr_cores <= MAX_CORES_IN_CCX) {
|
||||
return nr_cores;
|
||||
}
|
||||
/* Get the number of nodes required to build this config */
|
||||
nodes = nodes_in_socket(nr_cores);
|
||||
|
||||
/*
|
||||
* Divide the cores accros all the core complexes
|
||||
* Return rounded up value
|
||||
*/
|
||||
return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
|
||||
}
|
||||
|
||||
/* Encode cache info for CPUID[8000001D] */
|
||||
static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
|
||||
uint32_t *eax, uint32_t *ebx,
|
||||
uint32_t *ecx, uint32_t *edx)
|
||||
{
|
||||
uint32_t l3_cores;
|
||||
assert(cache->size == cache->line_size * cache->associativity *
|
||||
cache->partitions * cache->sets);
|
||||
|
||||
*eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
|
||||
(cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
|
||||
|
||||
/* L3 is shared among multiple cores */
|
||||
if (cache->level == 3) {
|
||||
l3_cores = cores_in_core_complex(cs->nr_cores);
|
||||
*eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
|
||||
} else {
|
||||
*eax |= ((cs->nr_threads - 1) << 14);
|
||||
}
|
||||
|
||||
assert(cache->line_size > 0);
|
||||
assert(cache->partitions > 0);
|
||||
assert(cache->associativity > 0);
|
||||
/* We don't implement fully-associative caches */
|
||||
assert(cache->associativity < cache->sets);
|
||||
*ebx = (cache->line_size - 1) |
|
||||
((cache->partitions - 1) << 12) |
|
||||
((cache->associativity - 1) << 22);
|
||||
|
||||
assert(cache->sets > 0);
|
||||
*ecx = cache->sets - 1;
|
||||
|
||||
*edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
|
||||
(cache->inclusive ? CACHE_INCLUSIVE : 0) |
|
||||
(cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Definitions of the hardcoded cache entries we expose:
|
||||
* These are legacy cache values. If there is a need to change any
|
||||
@ -1112,7 +1205,7 @@ struct X86CPUDefinition {
|
||||
};
|
||||
|
||||
static CPUCaches epyc_cache_info = {
|
||||
.l1d_cache = {
|
||||
.l1d_cache = &(CPUCacheInfo) {
|
||||
.type = DCACHE,
|
||||
.level = 1,
|
||||
.size = 32 * KiB,
|
||||
@ -1124,7 +1217,7 @@ static CPUCaches epyc_cache_info = {
|
||||
.self_init = 1,
|
||||
.no_invd_sharing = true,
|
||||
},
|
||||
.l1i_cache = {
|
||||
.l1i_cache = &(CPUCacheInfo) {
|
||||
.type = ICACHE,
|
||||
.level = 1,
|
||||
.size = 64 * KiB,
|
||||
@ -1136,7 +1229,7 @@ static CPUCaches epyc_cache_info = {
|
||||
.self_init = 1,
|
||||
.no_invd_sharing = true,
|
||||
},
|
||||
.l2_cache = {
|
||||
.l2_cache = &(CPUCacheInfo) {
|
||||
.type = UNIFIED_CACHE,
|
||||
.level = 2,
|
||||
.size = 512 * KiB,
|
||||
@ -1146,7 +1239,7 @@ static CPUCaches epyc_cache_info = {
|
||||
.sets = 1024,
|
||||
.lines_per_tag = 1,
|
||||
},
|
||||
.l3_cache = {
|
||||
.l3_cache = &(CPUCacheInfo) {
|
||||
.type = UNIFIED_CACHE,
|
||||
.level = 3,
|
||||
.size = 8 * MiB,
|
||||
@ -3340,9 +3433,8 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
|
||||
env->features[w] = def->features[w];
|
||||
}
|
||||
|
||||
/* Store Cache information from the X86CPUDefinition if available */
|
||||
env->cache_info = def->cache_info;
|
||||
cpu->legacy_cache = def->cache_info ? 0 : 1;
|
||||
/* legacy-cache defaults to 'off' if CPU model provides cache info */
|
||||
cpu->legacy_cache = !def->cache_info;
|
||||
|
||||
/* Special cases not set in the X86CPUDefinition structs: */
|
||||
/* TODO: in-kernel irqchip for hvf */
|
||||
@ -3693,21 +3785,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
||||
if (!cpu->enable_l3_cache) {
|
||||
*ecx = 0;
|
||||
} else {
|
||||
if (env->cache_info && !cpu->legacy_cache) {
|
||||
*ecx = cpuid2_cache_descriptor(&env->cache_info->l3_cache);
|
||||
} else {
|
||||
*ecx = cpuid2_cache_descriptor(&legacy_l3_cache);
|
||||
}
|
||||
}
|
||||
if (env->cache_info && !cpu->legacy_cache) {
|
||||
*edx = (cpuid2_cache_descriptor(&env->cache_info->l1d_cache) << 16) |
|
||||
(cpuid2_cache_descriptor(&env->cache_info->l1i_cache) << 8) |
|
||||
(cpuid2_cache_descriptor(&env->cache_info->l2_cache));
|
||||
} else {
|
||||
*edx = (cpuid2_cache_descriptor(&legacy_l1d_cache) << 16) |
|
||||
(cpuid2_cache_descriptor(&legacy_l1i_cache) << 8) |
|
||||
(cpuid2_cache_descriptor(&legacy_l2_cache_cpuid2));
|
||||
*ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
|
||||
}
|
||||
*edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
|
||||
(cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
|
||||
(cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
|
||||
break;
|
||||
case 4:
|
||||
/* cache info: needed for Core compatibility */
|
||||
@ -3720,35 +3802,27 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
||||
}
|
||||
} else {
|
||||
*eax = 0;
|
||||
CPUCacheInfo *l1d, *l1i, *l2, *l3;
|
||||
if (env->cache_info && !cpu->legacy_cache) {
|
||||
l1d = &env->cache_info->l1d_cache;
|
||||
l1i = &env->cache_info->l1i_cache;
|
||||
l2 = &env->cache_info->l2_cache;
|
||||
l3 = &env->cache_info->l3_cache;
|
||||
} else {
|
||||
l1d = &legacy_l1d_cache;
|
||||
l1i = &legacy_l1i_cache;
|
||||
l2 = &legacy_l2_cache;
|
||||
l3 = &legacy_l3_cache;
|
||||
}
|
||||
switch (count) {
|
||||
case 0: /* L1 dcache info */
|
||||
encode_cache_cpuid4(l1d, 1, cs->nr_cores,
|
||||
encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
|
||||
1, cs->nr_cores,
|
||||
eax, ebx, ecx, edx);
|
||||
break;
|
||||
case 1: /* L1 icache info */
|
||||
encode_cache_cpuid4(l1i, 1, cs->nr_cores,
|
||||
encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
|
||||
1, cs->nr_cores,
|
||||
eax, ebx, ecx, edx);
|
||||
break;
|
||||
case 2: /* L2 cache info */
|
||||
encode_cache_cpuid4(l2, cs->nr_threads, cs->nr_cores,
|
||||
encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
|
||||
cs->nr_threads, cs->nr_cores,
|
||||
eax, ebx, ecx, edx);
|
||||
break;
|
||||
case 3: /* L3 cache info */
|
||||
pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
|
||||
if (cpu->enable_l3_cache) {
|
||||
encode_cache_cpuid4(l3, (1 << pkg_offset), cs->nr_cores,
|
||||
encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
|
||||
(1 << pkg_offset), cs->nr_cores,
|
||||
eax, ebx, ecx, edx);
|
||||
break;
|
||||
}
|
||||
@ -3961,13 +4035,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
||||
(L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
|
||||
*ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
|
||||
(L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
|
||||
if (env->cache_info && !cpu->legacy_cache) {
|
||||
*ecx = encode_cache_cpuid80000005(&env->cache_info->l1d_cache);
|
||||
*edx = encode_cache_cpuid80000005(&env->cache_info->l1i_cache);
|
||||
} else {
|
||||
*ecx = encode_cache_cpuid80000005(&legacy_l1d_cache_amd);
|
||||
*edx = encode_cache_cpuid80000005(&legacy_l1i_cache_amd);
|
||||
}
|
||||
*ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
|
||||
*edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
|
||||
break;
|
||||
case 0x80000006:
|
||||
/* cache info (L2 cache) */
|
||||
@ -3983,17 +4052,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
||||
(L2_DTLB_4K_ENTRIES << 16) | \
|
||||
(AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
|
||||
(L2_ITLB_4K_ENTRIES);
|
||||
if (env->cache_info && !cpu->legacy_cache) {
|
||||
encode_cache_cpuid80000006(&env->cache_info->l2_cache,
|
||||
encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
|
||||
cpu->enable_l3_cache ?
|
||||
&env->cache_info->l3_cache : NULL,
|
||||
env->cache_info_amd.l3_cache : NULL,
|
||||
ecx, edx);
|
||||
} else {
|
||||
encode_cache_cpuid80000006(&legacy_l2_cache_amd,
|
||||
cpu->enable_l3_cache ?
|
||||
&legacy_l3_cache : NULL,
|
||||
ecx, edx);
|
||||
}
|
||||
break;
|
||||
case 0x80000007:
|
||||
*eax = 0;
|
||||
@ -4034,6 +4096,30 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
||||
*edx = 0;
|
||||
}
|
||||
break;
|
||||
case 0x8000001D:
|
||||
*eax = 0;
|
||||
switch (count) {
|
||||
case 0: /* L1 dcache info */
|
||||
encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
|
||||
eax, ebx, ecx, edx);
|
||||
break;
|
||||
case 1: /* L1 icache info */
|
||||
encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
|
||||
eax, ebx, ecx, edx);
|
||||
break;
|
||||
case 2: /* L2 cache info */
|
||||
encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
|
||||
eax, ebx, ecx, edx);
|
||||
break;
|
||||
case 3: /* L3 cache info */
|
||||
encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
|
||||
eax, ebx, ecx, edx);
|
||||
break;
|
||||
default: /* end of info */
|
||||
*eax = *ebx = *ecx = *edx = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 0xC0000000:
|
||||
*eax = env->cpuid_xlevel2;
|
||||
*ebx = 0;
|
||||
@ -4690,6 +4776,37 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
|
||||
cpu->phys_bits = 32;
|
||||
}
|
||||
}
|
||||
|
||||
/* Cache information initialization */
|
||||
if (!cpu->legacy_cache) {
|
||||
if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
|
||||
char *name = x86_cpu_class_get_model_name(xcc);
|
||||
error_setg(errp,
|
||||
"CPU model '%s' doesn't support legacy-cache=off", name);
|
||||
g_free(name);
|
||||
return;
|
||||
}
|
||||
env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
|
||||
*xcc->cpu_def->cache_info;
|
||||
} else {
|
||||
/* Build legacy cache information */
|
||||
env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
|
||||
env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
|
||||
env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
|
||||
env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
|
||||
|
||||
env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
|
||||
env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
|
||||
env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
|
||||
env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
|
||||
|
||||
env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
|
||||
env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
|
||||
env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
|
||||
env->cache_info_amd.l3_cache = &legacy_l3_cache;
|
||||
}
|
||||
|
||||
|
||||
cpu_exec_realizefn(cs, &local_err);
|
||||
if (local_err != NULL) {
|
||||
error_propagate(errp, local_err);
|
||||
@ -5173,11 +5290,10 @@ static Property x86_cpu_properties[] = {
|
||||
DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
|
||||
DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
|
||||
/*
|
||||
* lecacy_cache defaults to CPU model being chosen. This is set in
|
||||
* x86_cpu_load_def based on cache_info which is initialized in
|
||||
* builtin_x86_defs
|
||||
* lecacy_cache defaults to true unless the CPU model provides its
|
||||
* own cache information (see x86_cpu_load_def()).
|
||||
*/
|
||||
DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, false),
|
||||
DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
|
||||
|
||||
/*
|
||||
* From "Requirements for Implementing the Microsoft
|
||||
|
||||
@ -1098,10 +1098,10 @@ typedef struct CPUCacheInfo {
|
||||
|
||||
|
||||
typedef struct CPUCaches {
|
||||
CPUCacheInfo l1d_cache;
|
||||
CPUCacheInfo l1i_cache;
|
||||
CPUCacheInfo l2_cache;
|
||||
CPUCacheInfo l3_cache;
|
||||
CPUCacheInfo *l1d_cache;
|
||||
CPUCacheInfo *l1i_cache;
|
||||
CPUCacheInfo *l2_cache;
|
||||
CPUCacheInfo *l3_cache;
|
||||
} CPUCaches;
|
||||
|
||||
typedef struct CPUX86State {
|
||||
@ -1293,7 +1293,11 @@ typedef struct CPUX86State {
|
||||
/* Features that were explicitly enabled/disabled */
|
||||
FeatureWordArray user_features;
|
||||
uint32_t cpuid_model[12];
|
||||
CPUCaches *cache_info;
|
||||
/* Cache information for CPUID. When legacy-cache=on, the cache data
|
||||
* on each CPUID leaf will be different, because we keep compatibility
|
||||
* with old QEMU versions.
|
||||
*/
|
||||
CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
|
||||
|
||||
/* MTRRs */
|
||||
uint64_t mtrr_fixed[11];
|
||||
|
||||
@ -979,9 +979,32 @@ int kvm_arch_init_vcpu(CPUState *cs)
|
||||
}
|
||||
c = &cpuid_data.entries[cpuid_i++];
|
||||
|
||||
switch (i) {
|
||||
case 0x8000001d:
|
||||
/* Query for all AMD cache information leaves */
|
||||
for (j = 0; ; j++) {
|
||||
c->function = i;
|
||||
c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
|
||||
c->index = j;
|
||||
cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
|
||||
|
||||
if (c->eax == 0) {
|
||||
break;
|
||||
}
|
||||
if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
|
||||
fprintf(stderr, "cpuid_data is full, no space for "
|
||||
"cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
|
||||
abort();
|
||||
}
|
||||
c = &cpuid_data.entries[cpuid_i++];
|
||||
}
|
||||
break;
|
||||
default:
|
||||
c->function = i;
|
||||
c->flags = 0;
|
||||
cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Call Centaur's CPUID instructions they are supported. */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user