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target/riscv: Update the ePMP CSR address

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Update the ePMP CSRs to match the 0.9.3 ePMP spec
6145574723/Smepmp/Smepmp.pdf

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 28c908de60b9b04fa20e63d113885c98586053f3.1630543194.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2021-09-02 10:40:10 +10:00
parent 326ff8dd09
commit a44da25aa6
2 changed files with 3 additions and 2 deletions
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1
target/riscv/cpu.c
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@ -599,6 +599,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),

4
target/riscv/cpu_bits.h
View File

@ -210,8 +210,8 @@
#define CSR_MTVAL2 0x34b
/* Enhanced Physical Memory Protection (ePMP) */
#define CSR_MSECCFG 0x390
#define CSR_MSECCFGH 0x391
#define CSR_MSECCFG 0x747
#define CSR_MSECCFGH 0x757
/* Physical Memory Protection */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1