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target/riscv: Hoist second stage mode change to callers

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Move the check from the top of get_physical_address to
the two callers, where passing mmu_idx makes no sense.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-19-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-19-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2023-04-12 13:43:26 +02:00 committed by Alistair Francis
parent eaecd473ca
commit a427c83633
1 changed files with 2 additions and 10 deletions
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12
target/riscv/cpu_helper.c
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@ -777,14 +777,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
use_background = true;
}
if (first_stage == false) {
/*
* We are in stage 2 translation, this is similar to stage 1.
* Stage 2 is always taken as U-mode
*/
mode = PRV_U;
}
if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) {
*physical = addr;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@ -890,7 +882,7 @@ restart:
/* Do the second stage translation on the base PTE address. */
int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
base, NULL, MMU_DATA_LOAD,
mmu_idx, false, true,
MMUIdx_U, false, true,
is_debug);
if (vbase_ret != TRANSLATE_SUCCESS) {
@ -1271,7 +1263,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
im_address = pa;
ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
access_type, mmu_idx, false, true,
access_type, MMUIdx_U, false, true,
false);
qemu_log_mask(CPU_LOG_MMU,