target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}
- modify check for mcounteren to work in all less-privilege mode - modify check for scounteren to work only when S mode is enabled - distinguish the exception type raised by check for scounteren between U and VU mode Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220817083756.12471-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -98,17 +98,22 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
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skip_ext_pmu_check:
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skip_ext_pmu_check:
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if (((env->priv == PRV_S) && (!get_field(env->mcounteren, ctr_mask))) ||
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if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) {
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((env->priv == PRV_U) && (!get_field(env->scounteren, ctr_mask)))) {
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return RISCV_EXCP_ILLEGAL_INST;
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return RISCV_EXCP_ILLEGAL_INST;
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}
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}
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if (riscv_cpu_virt_enabled(env)) {
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if (riscv_cpu_virt_enabled(env)) {
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if (!get_field(env->hcounteren, ctr_mask) &&
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if (!get_field(env->hcounteren, ctr_mask) ||
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get_field(env->mcounteren, ctr_mask)) {
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(env->priv == PRV_U && !get_field(env->scounteren, ctr_mask))) {
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return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
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return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
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}
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}
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}
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}
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if (riscv_has_ext(env, RVS) && env->priv == PRV_U &&
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!get_field(env->scounteren, ctr_mask)) {
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return RISCV_EXCP_ILLEGAL_INST;
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}
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#endif
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#endif
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return RISCV_EXCP_NONE;
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return RISCV_EXCP_NONE;
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}
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}
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