hw/nvme: use symbolic names for registers
Add the NvmeBarRegs enum and use these instead of explicit register offsets. Signed-off-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Gollu Appalanaidu <anaidu.gollu@samsung.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Keith Busch <kbusch@kernel.org>
This commit is contained in:
Klaus Jensen
parent
5d45edbeac
commit
a316aa50e6
@ -5740,7 +5740,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
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}
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switch (offset) {
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case 0xc: /* INTMS */
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case NVME_REG_INTMS:
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if (unlikely(msix_enabled(&(n->parent_obj)))) {
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NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix,
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"undefined access to interrupt mask set"
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@ -5752,7 +5752,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
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trace_pci_nvme_mmio_intm_set(data & 0xffffffff, n->bar.intmc);
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nvme_irq_check(n);
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break;
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case 0x10: /* INTMC */
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case NVME_REG_INTMC:
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if (unlikely(msix_enabled(&(n->parent_obj)))) {
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NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix,
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"undefined access to interrupt mask clr"
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@ -5764,7 +5764,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
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trace_pci_nvme_mmio_intm_clr(data & 0xffffffff, n->bar.intmc);
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nvme_irq_check(n);
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break;
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case 0x14: /* CC */
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case NVME_REG_CC:
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trace_pci_nvme_mmio_cfg(data & 0xffffffff);
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/* Windows first sends data, then sends enable bit */
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if (!NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc) &&
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@ -5798,7 +5798,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
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n->bar.cc = data;
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}
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break;
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case 0x1c: /* CSTS */
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case NVME_REG_CSTS:
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if (data & (1 << 4)) {
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NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ssreset_w1c_unsupported,
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"attempted to W1C CSTS.NSSRO"
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@ -5809,7 +5809,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
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" of controller status");
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}
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break;
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case 0x20: /* NSSR */
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case NVME_REG_NSSR:
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if (data == 0x4e564d65) {
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trace_pci_nvme_ub_mmiowr_ssreset_unsupported();
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} else {
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@ -5817,38 +5817,38 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
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return;
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}
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break;
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case 0x24: /* AQA */
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case NVME_REG_AQA:
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n->bar.aqa = data & 0xffffffff;
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trace_pci_nvme_mmio_aqattr(data & 0xffffffff);
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break;
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case 0x28: /* ASQ */
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case NVME_REG_ASQ:
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n->bar.asq = size == 8 ? data :
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(n->bar.asq & ~0xffffffffULL) | (data & 0xffffffff);
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trace_pci_nvme_mmio_asqaddr(data);
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break;
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case 0x2c: /* ASQ hi */
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case NVME_REG_ASQ + 4:
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n->bar.asq = (n->bar.asq & 0xffffffff) | (data << 32);
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trace_pci_nvme_mmio_asqaddr_hi(data, n->bar.asq);
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break;
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case 0x30: /* ACQ */
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case NVME_REG_ACQ:
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trace_pci_nvme_mmio_acqaddr(data);
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n->bar.acq = size == 8 ? data :
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(n->bar.acq & ~0xffffffffULL) | (data & 0xffffffff);
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break;
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case 0x34: /* ACQ hi */
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case NVME_REG_ACQ + 4:
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n->bar.acq = (n->bar.acq & 0xffffffff) | (data << 32);
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trace_pci_nvme_mmio_acqaddr_hi(data, n->bar.acq);
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break;
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case 0x38: /* CMBLOC */
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case NVME_REG_CMBLOC:
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NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbloc_reserved,
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"invalid write to reserved CMBLOC"
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" when CMBSZ is zero, ignored");
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return;
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case 0x3C: /* CMBSZ */
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case NVME_REG_CMBSZ:
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NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbsz_readonly,
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"invalid write to read only CMBSZ, ignored");
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return;
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case 0x50: /* CMBMSC */
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case NVME_REG_CMBMSC:
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if (!NVME_CAP_CMBS(n->bar.cap)) {
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return;
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}
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@ -5876,15 +5876,15 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
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}
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return;
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case 0x54: /* CMBMSC hi */
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case NVME_REG_CMBMSC + 4:
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n->bar.cmbmsc = (n->bar.cmbmsc & 0xffffffff) | (data << 32);
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return;
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case 0xe00: /* PMRCAP */
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case NVME_REG_PMRCAP:
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NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrcap_readonly,
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"invalid write to PMRCAP register, ignored");
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return;
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case 0xe04: /* PMRCTL */
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case NVME_REG_PMRCTL:
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if (!NVME_CAP_PMRS(n->bar.cap)) {
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return;
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}
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@ -5899,19 +5899,19 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
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n->pmr.cmse = false;
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}
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return;
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case 0xe08: /* PMRSTS */
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case NVME_REG_PMRSTS:
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NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrsts_readonly,
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"invalid write to PMRSTS register, ignored");
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return;
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case 0xe0C: /* PMREBS */
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case NVME_REG_PMREBS:
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NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrebs_readonly,
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"invalid write to PMREBS register, ignored");
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return;
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case 0xe10: /* PMRSWTP */
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case NVME_REG_PMRSWTP:
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NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrswtp_readonly,
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"invalid write to PMRSWTP register, ignored");
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return;
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case 0xe14: /* PMRMSCL */
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case NVME_REG_PMRMSCL:
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if (!NVME_CAP_PMRS(n->bar.cap)) {
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return;
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}
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@ -5933,7 +5933,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
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}
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return;
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case 0xe18: /* PMRMSCU */
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case NVME_REG_PMRMSCU:
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if (!NVME_CAP_PMRS(n->bar.cap)) {
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return;
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}
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@ -5975,7 +5975,7 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size)
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* from PMRSTS should ensure prior writes
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* made it to persistent media
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*/
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if (addr == 0xe08 &&
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if (addr == NVME_REG_PMRSTS &&
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(NVME_PMRCAP_PMRWBM(n->bar.pmrcap) & 0x02)) {
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memory_region_msync(&n->pmr.dev->mr, 0, n->pmr.dev->size);
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}
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@ -9,7 +9,7 @@ typedef struct QEMU_PACKED NvmeBar {
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uint32_t cc;
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uint8_t rsvd24[4];
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uint32_t csts;
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uint32_t nssrc;
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uint32_t nssr;
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uint32_t aqa;
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uint64_t asq;
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uint64_t acq;
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@ -31,6 +31,33 @@ typedef struct QEMU_PACKED NvmeBar {
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uint8_t css[484];
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} NvmeBar;
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enum NvmeBarRegs {
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NVME_REG_CAP = offsetof(NvmeBar, cap),
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NVME_REG_VS = offsetof(NvmeBar, vs),
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NVME_REG_INTMS = offsetof(NvmeBar, intms),
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NVME_REG_INTMC = offsetof(NvmeBar, intmc),
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NVME_REG_CC = offsetof(NvmeBar, cc),
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NVME_REG_CSTS = offsetof(NvmeBar, csts),
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NVME_REG_NSSR = offsetof(NvmeBar, nssr),
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NVME_REG_AQA = offsetof(NvmeBar, aqa),
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NVME_REG_ASQ = offsetof(NvmeBar, asq),
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NVME_REG_ACQ = offsetof(NvmeBar, acq),
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NVME_REG_CMBLOC = offsetof(NvmeBar, cmbloc),
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NVME_REG_CMBSZ = offsetof(NvmeBar, cmbsz),
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NVME_REG_BPINFO = offsetof(NvmeBar, bpinfo),
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NVME_REG_BPRSEL = offsetof(NvmeBar, bprsel),
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NVME_REG_BPMBL = offsetof(NvmeBar, bpmbl),
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NVME_REG_CMBMSC = offsetof(NvmeBar, cmbmsc),
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NVME_REG_CMBSTS = offsetof(NvmeBar, cmbsts),
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NVME_REG_PMRCAP = offsetof(NvmeBar, pmrcap),
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NVME_REG_PMRCTL = offsetof(NvmeBar, pmrctl),
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NVME_REG_PMRSTS = offsetof(NvmeBar, pmrsts),
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NVME_REG_PMREBS = offsetof(NvmeBar, pmrebs),
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NVME_REG_PMRSWTP = offsetof(NvmeBar, pmrswtp),
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NVME_REG_PMRMSCL = offsetof(NvmeBar, pmrmscl),
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NVME_REG_PMRMSCU = offsetof(NvmeBar, pmrmscu),
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};
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enum NvmeCapShift {
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CAP_MQES_SHIFT = 0,
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CAP_CQR_SHIFT = 16,
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