- Add FTOU, CRCN, FTOHP, and HPTOF insns
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This commit is contained in:
commit
a3108b2d92
@ -16,6 +16,7 @@
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*/
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*/
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#include "qemu/osdep.h"
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/sysbus.h"
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#include "hw/sysbus.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties.h"
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#include "hw/tricore/tricore_testdevice.h"
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#include "hw/tricore/tricore_testdevice.h"
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@ -23,6 +24,9 @@
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static void tricore_testdevice_write(void *opaque, hwaddr offset,
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static void tricore_testdevice_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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uint64_t value, unsigned size)
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{
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{
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if (value != 0) {
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qemu_log_mask(LOG_GUEST_ERROR, "Test %" PRIu64 " failed!\n", value);
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}
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exit(value);
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exit(value);
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}
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}
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@ -30,150 +30,25 @@ typedef struct CPUArchState {
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/* GPR Register */
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/* GPR Register */
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uint32_t gpr_a[16];
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uint32_t gpr_a[16];
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uint32_t gpr_d[16];
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uint32_t gpr_d[16];
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/* CSFR Register */
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uint32_t PCXI;
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/* Frequently accessed PSW_USB bits are stored separately for efficiency.
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/* Frequently accessed PSW_USB bits are stored separately for efficiency.
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This contains all the other bits. Use psw_{read,write} to access
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This contains all the other bits. Use psw_{read,write} to access
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the whole PSW. */
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the whole PSW. */
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uint32_t PSW;
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uint32_t PSW;
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/* PSW flag cache for faster execution */
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/* PSW flag cache for faster execution
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*/
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uint32_t PSW_USB_C;
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uint32_t PSW_USB_C;
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uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */
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uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */
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uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */
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uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */
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uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
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uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
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uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
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uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
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uint32_t PC;
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#define R(ADDR, NAME, FEATURE) uint32_t NAME;
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uint32_t SYSCON;
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#define A(ADDR, NAME, FEATURE) uint32_t NAME;
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uint32_t CPU_ID;
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#define E(ADDR, NAME, FEATURE) uint32_t NAME;
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uint32_t CORE_ID;
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#include "csfr.h.inc"
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uint32_t BIV;
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#undef R
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uint32_t BTV;
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#undef A
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uint32_t ISP;
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#undef E
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uint32_t ICR;
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uint32_t FCX;
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uint32_t LCX;
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uint32_t COMPAT;
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/* Mem Protection Register */
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uint32_t DPR0_0L;
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uint32_t DPR0_0U;
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uint32_t DPR0_1L;
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uint32_t DPR0_1U;
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uint32_t DPR0_2L;
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uint32_t DPR0_2U;
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uint32_t DPR0_3L;
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uint32_t DPR0_3U;
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uint32_t DPR1_0L;
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uint32_t DPR1_0U;
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uint32_t DPR1_1L;
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uint32_t DPR1_1U;
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uint32_t DPR1_2L;
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uint32_t DPR1_2U;
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uint32_t DPR1_3L;
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uint32_t DPR1_3U;
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uint32_t DPR2_0L;
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uint32_t DPR2_0U;
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uint32_t DPR2_1L;
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uint32_t DPR2_1U;
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uint32_t DPR2_2L;
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uint32_t DPR2_2U;
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uint32_t DPR2_3L;
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uint32_t DPR2_3U;
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uint32_t DPR3_0L;
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uint32_t DPR3_0U;
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uint32_t DPR3_1L;
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uint32_t DPR3_1U;
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uint32_t DPR3_2L;
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uint32_t DPR3_2U;
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uint32_t DPR3_3L;
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uint32_t DPR3_3U;
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uint32_t CPR0_0L;
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uint32_t CPR0_0U;
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uint32_t CPR0_1L;
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uint32_t CPR0_1U;
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uint32_t CPR0_2L;
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uint32_t CPR0_2U;
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uint32_t CPR0_3L;
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uint32_t CPR0_3U;
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uint32_t CPR1_0L;
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uint32_t CPR1_0U;
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uint32_t CPR1_1L;
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uint32_t CPR1_1U;
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uint32_t CPR1_2L;
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uint32_t CPR1_2U;
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uint32_t CPR1_3L;
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uint32_t CPR1_3U;
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uint32_t CPR2_0L;
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uint32_t CPR2_0U;
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uint32_t CPR2_1L;
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uint32_t CPR2_1U;
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uint32_t CPR2_2L;
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uint32_t CPR2_2U;
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uint32_t CPR2_3L;
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uint32_t CPR2_3U;
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uint32_t CPR3_0L;
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uint32_t CPR3_0U;
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uint32_t CPR3_1L;
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uint32_t CPR3_1U;
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uint32_t CPR3_2L;
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uint32_t CPR3_2U;
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uint32_t CPR3_3L;
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uint32_t CPR3_3U;
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uint32_t DPM0;
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uint32_t DPM1;
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uint32_t DPM2;
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uint32_t DPM3;
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uint32_t CPM0;
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uint32_t CPM1;
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uint32_t CPM2;
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uint32_t CPM3;
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/* Memory Management Registers */
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uint32_t MMU_CON;
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uint32_t MMU_ASI;
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uint32_t MMU_TVA;
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uint32_t MMU_TPA;
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uint32_t MMU_TPX;
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uint32_t MMU_TFA;
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/* {1.3.1 only */
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uint32_t BMACON;
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uint32_t SMACON;
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uint32_t DIEAR;
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uint32_t DIETR;
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uint32_t CCDIER;
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uint32_t MIECON;
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uint32_t PIEAR;
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uint32_t PIETR;
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uint32_t CCPIER;
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/*} */
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/* Debug Registers */
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uint32_t DBGSR;
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uint32_t EXEVT;
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uint32_t CREVT;
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uint32_t SWEVT;
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uint32_t TR0EVT;
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uint32_t TR1EVT;
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uint32_t DMS;
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uint32_t DCX;
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uint32_t DBGTCR;
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uint32_t CCTRL;
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uint32_t CCNT;
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uint32_t ICNT;
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uint32_t M1CNT;
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uint32_t M2CNT;
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uint32_t M3CNT;
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/* Floating Point Registers */
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/* Floating Point Registers */
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float_status fp_status;
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float_status fp_status;
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@ -373,6 +373,80 @@ uint32_t helper_ftoi(CPUTriCoreState *env, uint32_t arg)
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return (uint32_t)result;
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return (uint32_t)result;
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}
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}
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uint32_t helper_hptof(CPUTriCoreState *env, uint32_t arg)
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{
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float16 f_arg = make_float16(arg);
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uint32_t result = 0;
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int32_t flags = 0;
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/*
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* if we have any NAN we need to move the top 2 and lower 8 input mantissa
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* bits to the top 2 and lower 8 output mantissa bits respectively.
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* Softfloat on the other hand uses the top 10 mantissa bits.
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*/
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if (float16_is_any_nan(f_arg)) {
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if (float16_is_signaling_nan(f_arg, &env->fp_status)) {
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flags |= float_flag_invalid;
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}
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result = 0;
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result = float32_set_sign(result, f_arg >> 15);
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result = deposit32(result, 23, 8, 0xff);
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result = deposit32(result, 21, 2, extract32(f_arg, 8, 2));
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result = deposit32(result, 0, 8, extract32(f_arg, 0, 8));
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} else {
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set_flush_inputs_to_zero(0, &env->fp_status);
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result = float16_to_float32(f_arg, true, &env->fp_status);
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set_flush_inputs_to_zero(1, &env->fp_status);
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flags = f_get_excp_flags(env);
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}
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if (flags) {
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f_update_psw_flags(env, flags);
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} else {
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env->FPU_FS = 0;
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}
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return result;
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}
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uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
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{
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float32 f_arg = make_float32(arg);
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uint32_t result = 0;
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int32_t flags = 0;
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/*
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* if we have any NAN we need to move the top 2 and lower 8 input mantissa
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* bits to the top 2 and lower 8 output mantissa bits respectively.
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* Softfloat on the other hand uses the top 10 mantissa bits.
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*/
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if (float32_is_any_nan(f_arg)) {
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if (float32_is_signaling_nan(f_arg, &env->fp_status)) {
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flags |= float_flag_invalid;
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}
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result = float16_set_sign(result, arg >> 31);
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result = deposit32(result, 10, 5, 0x1f);
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result = deposit32(result, 8, 2, extract32(arg, 21, 2));
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result = deposit32(result, 0, 8, extract32(arg, 0, 8));
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|
if (extract32(result, 0, 10) == 0) {
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|
result |= (1 << 8);
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|
}
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|
} else {
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|
set_flush_to_zero(0, &env->fp_status);
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|
result = float32_to_float16(f_arg, true, &env->fp_status);
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|
set_flush_to_zero(1, &env->fp_status);
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|
flags = f_get_excp_flags(env);
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|
}
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|
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|
if (flags) {
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|
f_update_psw_flags(env, flags);
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|
} else {
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|
env->FPU_FS = 0;
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|
}
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|
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|
return result;
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|
}
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|
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uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg)
|
uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg)
|
||||||
{
|
{
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||||||
float32 f_result;
|
float32 f_result;
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@ -429,6 +503,38 @@ uint32_t helper_ftoiz(CPUTriCoreState *env, uint32_t arg)
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|||||||
return result;
|
return result;
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}
|
}
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|
|
||||||
|
uint32_t helper_ftou(CPUTriCoreState *env, uint32_t arg)
|
||||||
|
{
|
||||||
|
float32 f_arg = make_float32(arg);
|
||||||
|
uint32_t result;
|
||||||
|
int32_t flags = 0;
|
||||||
|
|
||||||
|
result = float32_to_uint32(f_arg, &env->fp_status);
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||||||
|
|
||||||
|
flags = f_get_excp_flags(env);
|
||||||
|
if (flags & float_flag_invalid) {
|
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|
flags &= ~float_flag_inexact;
|
||||||
|
if (float32_is_any_nan(f_arg)) {
|
||||||
|
result = 0;
|
||||||
|
}
|
||||||
|
/*
|
||||||
|
* we need to check arg < 0.0 before rounding as TriCore needs to raise
|
||||||
|
* float_flag_invalid as well. For instance, when we have a negative
|
||||||
|
* exponent and sign, softfloat would only raise float_flat_inexact.
|
||||||
|
*/
|
||||||
|
} else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
|
||||||
|
flags = float_flag_invalid;
|
||||||
|
result = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (flags) {
|
||||||
|
f_update_psw_flags(env, flags);
|
||||||
|
} else {
|
||||||
|
env->FPU_FS = 0;
|
||||||
|
}
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
|
uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
|
||||||
{
|
{
|
||||||
float32 f_arg = make_float32(arg);
|
float32 f_arg = make_float32(arg);
|
||||||
@ -443,6 +549,11 @@ uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
|
|||||||
if (float32_is_any_nan(f_arg)) {
|
if (float32_is_any_nan(f_arg)) {
|
||||||
result = 0;
|
result = 0;
|
||||||
}
|
}
|
||||||
|
/*
|
||||||
|
* we need to check arg < 0.0 before rounding as TriCore needs to raise
|
||||||
|
* float_flag_invalid as well. For instance, when we have a negative
|
||||||
|
* exponent and sign, softfloat would only raise float_flat_inexact.
|
||||||
|
*/
|
||||||
} else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
|
} else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
|
||||||
flags = float_flag_invalid;
|
flags = float_flag_invalid;
|
||||||
result = 0;
|
result = 0;
|
||||||
|
@ -120,16 +120,31 @@ void tricore_cpu_list(void)
|
|||||||
|
|
||||||
void fpu_set_state(CPUTriCoreState *env)
|
void fpu_set_state(CPUTriCoreState *env)
|
||||||
{
|
{
|
||||||
set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status);
|
switch (extract32(env->PSW, 24, 2)) {
|
||||||
|
case 0:
|
||||||
|
set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
set_float_rounding_mode(float_round_up, &env->fp_status);
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
set_float_rounding_mode(float_round_down, &env->fp_status);
|
||||||
|
break;
|
||||||
|
case 3:
|
||||||
|
set_float_rounding_mode(float_round_to_zero, &env->fp_status);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
set_flush_inputs_to_zero(1, &env->fp_status);
|
set_flush_inputs_to_zero(1, &env->fp_status);
|
||||||
set_flush_to_zero(1, &env->fp_status);
|
set_flush_to_zero(1, &env->fp_status);
|
||||||
|
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
|
||||||
set_default_nan_mode(1, &env->fp_status);
|
set_default_nan_mode(1, &env->fp_status);
|
||||||
}
|
}
|
||||||
|
|
||||||
uint32_t psw_read(CPUTriCoreState *env)
|
uint32_t psw_read(CPUTriCoreState *env)
|
||||||
{
|
{
|
||||||
/* clear all USB bits */
|
/* clear all USB bits */
|
||||||
env->PSW &= 0x6ffffff;
|
env->PSW &= 0x7ffffff;
|
||||||
/* now set them from the cache */
|
/* now set them from the cache */
|
||||||
env->PSW |= ((env->PSW_USB_C != 0) << 31);
|
env->PSW |= ((env->PSW_USB_C != 0) << 31);
|
||||||
env->PSW |= ((env->PSW_USB_V & (1 << 31)) >> 1);
|
env->PSW |= ((env->PSW_USB_V & (1 << 31)) >> 1);
|
||||||
|
@ -111,9 +111,12 @@ DEF_HELPER_4(fmsub, i32, env, i32, i32, i32)
|
|||||||
DEF_HELPER_3(fcmp, i32, env, i32, i32)
|
DEF_HELPER_3(fcmp, i32, env, i32, i32)
|
||||||
DEF_HELPER_2(qseed, i32, env, i32)
|
DEF_HELPER_2(qseed, i32, env, i32)
|
||||||
DEF_HELPER_2(ftoi, i32, env, i32)
|
DEF_HELPER_2(ftoi, i32, env, i32)
|
||||||
|
DEF_HELPER_2(ftohp, i32, env, i32)
|
||||||
|
DEF_HELPER_2(hptof, i32, env, i32)
|
||||||
DEF_HELPER_2(itof, i32, env, i32)
|
DEF_HELPER_2(itof, i32, env, i32)
|
||||||
DEF_HELPER_2(utof, i32, env, i32)
|
DEF_HELPER_2(utof, i32, env, i32)
|
||||||
DEF_HELPER_2(ftoiz, i32, env, i32)
|
DEF_HELPER_2(ftoiz, i32, env, i32)
|
||||||
|
DEF_HELPER_2(ftou, i32, env, i32)
|
||||||
DEF_HELPER_2(ftouz, i32, env, i32)
|
DEF_HELPER_2(ftouz, i32, env, i32)
|
||||||
DEF_HELPER_2(updfl, void, env, i32)
|
DEF_HELPER_2(updfl, void, env, i32)
|
||||||
/* dvinit */
|
/* dvinit */
|
||||||
@ -134,6 +137,7 @@ DEF_HELPER_FLAGS_5(mulr_h, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32, i32)
|
|||||||
DEF_HELPER_FLAGS_2(crc32b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
DEF_HELPER_FLAGS_2(crc32b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||||
DEF_HELPER_FLAGS_2(crc32_be, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
DEF_HELPER_FLAGS_2(crc32_be, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||||
DEF_HELPER_FLAGS_2(crc32_le, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
DEF_HELPER_FLAGS_2(crc32_le, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||||
|
DEF_HELPER_FLAGS_3(crcn, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
|
||||||
DEF_HELPER_FLAGS_2(shuffle, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
DEF_HELPER_FLAGS_2(shuffle, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||||
/* CSA */
|
/* CSA */
|
||||||
DEF_HELPER_2(call, void, env, i32)
|
DEF_HELPER_2(call, void, env, i32)
|
||||||
|
@ -2308,6 +2308,69 @@ uint32_t helper_crc32_le(uint32_t arg0, uint32_t arg1)
|
|||||||
return crc32(arg1, buf, 4);
|
return crc32(arg1, buf, 4);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static uint32_t crc_div(uint32_t crc_in, uint32_t data, uint32_t gen,
|
||||||
|
uint32_t n, uint32_t m)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
|
||||||
|
data = data << n;
|
||||||
|
for (i = 0; i < m; i++) {
|
||||||
|
if (crc_in & (1u << (n - 1))) {
|
||||||
|
crc_in <<= 1;
|
||||||
|
if (data & (1u << (m - 1))) {
|
||||||
|
crc_in++;
|
||||||
|
}
|
||||||
|
crc_in ^= gen;
|
||||||
|
} else {
|
||||||
|
crc_in <<= 1;
|
||||||
|
if (data & (1u << (m - 1))) {
|
||||||
|
crc_in++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
data <<= 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return crc_in;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t helper_crcn(uint32_t arg0, uint32_t arg1, uint32_t arg2)
|
||||||
|
{
|
||||||
|
uint32_t crc_out, crc_in;
|
||||||
|
uint32_t n = extract32(arg0, 12, 4) + 1;
|
||||||
|
uint32_t gen = extract32(arg0, 16, n);
|
||||||
|
uint32_t inv = extract32(arg0, 9, 1);
|
||||||
|
uint32_t le = extract32(arg0, 8, 1);
|
||||||
|
uint32_t m = extract32(arg0, 0, 3) + 1;
|
||||||
|
uint32_t data = extract32(arg1, 0, m);
|
||||||
|
uint32_t seed = extract32(arg2, 0, n);
|
||||||
|
|
||||||
|
if (le == 1) {
|
||||||
|
if (m == 0) {
|
||||||
|
data = 0;
|
||||||
|
} else {
|
||||||
|
data = revbit32(data) >> (32 - m);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (inv == 1) {
|
||||||
|
seed = ~seed;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (m > n) {
|
||||||
|
crc_in = (data >> (m - n)) ^ seed;
|
||||||
|
} else {
|
||||||
|
crc_in = (data << (n - m)) ^ seed;
|
||||||
|
}
|
||||||
|
|
||||||
|
crc_out = crc_div(crc_in, data, gen, n, m);
|
||||||
|
|
||||||
|
if (inv) {
|
||||||
|
crc_out = ~crc_out;
|
||||||
|
}
|
||||||
|
|
||||||
|
return extract32(crc_out, 0, n);
|
||||||
|
}
|
||||||
|
|
||||||
uint32_t helper_shuffle(uint32_t arg0, uint32_t arg1)
|
uint32_t helper_shuffle(uint32_t arg0, uint32_t arg1)
|
||||||
{
|
{
|
||||||
uint32_t resb;
|
uint32_t resb;
|
||||||
@ -2395,7 +2458,7 @@ static bool cdc_zero(target_ulong *psw)
|
|||||||
return count == 0;
|
return count == 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void save_context_upper(CPUTriCoreState *env, int ea)
|
static void save_context_upper(CPUTriCoreState *env, target_ulong ea)
|
||||||
{
|
{
|
||||||
cpu_stl_data(env, ea, env->PCXI);
|
cpu_stl_data(env, ea, env->PCXI);
|
||||||
cpu_stl_data(env, ea+4, psw_read(env));
|
cpu_stl_data(env, ea+4, psw_read(env));
|
||||||
@ -2415,7 +2478,7 @@ static void save_context_upper(CPUTriCoreState *env, int ea)
|
|||||||
cpu_stl_data(env, ea+60, env->gpr_d[15]);
|
cpu_stl_data(env, ea+60, env->gpr_d[15]);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void save_context_lower(CPUTriCoreState *env, int ea)
|
static void save_context_lower(CPUTriCoreState *env, target_ulong ea)
|
||||||
{
|
{
|
||||||
cpu_stl_data(env, ea, env->PCXI);
|
cpu_stl_data(env, ea, env->PCXI);
|
||||||
cpu_stl_data(env, ea+4, env->gpr_a[11]);
|
cpu_stl_data(env, ea+4, env->gpr_a[11]);
|
||||||
@ -2435,7 +2498,7 @@ static void save_context_lower(CPUTriCoreState *env, int ea)
|
|||||||
cpu_stl_data(env, ea+60, env->gpr_d[7]);
|
cpu_stl_data(env, ea+60, env->gpr_d[7]);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void restore_context_upper(CPUTriCoreState *env, int ea,
|
static void restore_context_upper(CPUTriCoreState *env, target_ulong ea,
|
||||||
target_ulong *new_PCXI, target_ulong *new_PSW)
|
target_ulong *new_PCXI, target_ulong *new_PSW)
|
||||||
{
|
{
|
||||||
*new_PCXI = cpu_ldl_data(env, ea);
|
*new_PCXI = cpu_ldl_data(env, ea);
|
||||||
@ -2456,7 +2519,7 @@ static void restore_context_upper(CPUTriCoreState *env, int ea,
|
|||||||
env->gpr_d[15] = cpu_ldl_data(env, ea+60);
|
env->gpr_d[15] = cpu_ldl_data(env, ea+60);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void restore_context_lower(CPUTriCoreState *env, int ea,
|
static void restore_context_lower(CPUTriCoreState *env, target_ulong ea,
|
||||||
target_ulong *ra, target_ulong *pcxi)
|
target_ulong *ra, target_ulong *pcxi)
|
||||||
{
|
{
|
||||||
*pcxi = cpu_ldl_data(env, ea);
|
*pcxi = cpu_ldl_data(env, ea);
|
||||||
@ -2700,26 +2763,26 @@ void helper_rfm(CPUTriCoreState *env)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void helper_ldlcx(CPUTriCoreState *env, uint32_t ea)
|
void helper_ldlcx(CPUTriCoreState *env, target_ulong ea)
|
||||||
{
|
{
|
||||||
uint32_t dummy;
|
uint32_t dummy;
|
||||||
/* insn doesn't load PCXI and RA */
|
/* insn doesn't load PCXI and RA */
|
||||||
restore_context_lower(env, ea, &dummy, &dummy);
|
restore_context_lower(env, ea, &dummy, &dummy);
|
||||||
}
|
}
|
||||||
|
|
||||||
void helper_lducx(CPUTriCoreState *env, uint32_t ea)
|
void helper_lducx(CPUTriCoreState *env, target_ulong ea)
|
||||||
{
|
{
|
||||||
uint32_t dummy;
|
uint32_t dummy;
|
||||||
/* insn doesn't load PCXI and PSW */
|
/* insn doesn't load PCXI and PSW */
|
||||||
restore_context_upper(env, ea, &dummy, &dummy);
|
restore_context_upper(env, ea, &dummy, &dummy);
|
||||||
}
|
}
|
||||||
|
|
||||||
void helper_stlcx(CPUTriCoreState *env, uint32_t ea)
|
void helper_stlcx(CPUTriCoreState *env, target_ulong ea)
|
||||||
{
|
{
|
||||||
save_context_lower(env, ea);
|
save_context_lower(env, ea);
|
||||||
}
|
}
|
||||||
|
|
||||||
void helper_stucx(CPUTriCoreState *env, uint32_t ea)
|
void helper_stucx(CPUTriCoreState *env, target_ulong ea)
|
||||||
{
|
{
|
||||||
save_context_upper(env, ea);
|
save_context_upper(env, ea);
|
||||||
}
|
}
|
||||||
|
@ -5310,8 +5310,11 @@ static void decode_rcpw_insert(DisasContext *ctx)
|
|||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case OPC2_32_RCPW_INSERT:
|
case OPC2_32_RCPW_INSERT:
|
||||||
|
/* tcg_gen_deposit_tl() does not handle the case of width = 0 */
|
||||||
|
if (width == 0) {
|
||||||
|
tcg_gen_mov_tl(cpu_gpr_d[r2], cpu_gpr_d[r1]);
|
||||||
/* if pos + width > 32 undefined result */
|
/* if pos + width > 32 undefined result */
|
||||||
if (pos + width <= 32) {
|
} else if (pos + width <= 32) {
|
||||||
temp = tcg_constant_i32(const4);
|
temp = tcg_constant_i32(const4);
|
||||||
tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
|
tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
|
||||||
}
|
}
|
||||||
@ -6260,6 +6263,20 @@ static void decode_rr_divide(DisasContext *ctx)
|
|||||||
case OPC2_32_RR_DIV_F:
|
case OPC2_32_RR_DIV_F:
|
||||||
gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
|
gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
|
||||||
break;
|
break;
|
||||||
|
case OPC2_32_RR_FTOHP:
|
||||||
|
if (has_feature(ctx, TRICORE_FEATURE_162)) {
|
||||||
|
gen_helper_ftohp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
|
||||||
|
} else {
|
||||||
|
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case OPC2_32_RR_HPTOF:
|
||||||
|
if (has_feature(ctx, TRICORE_FEATURE_162)) {
|
||||||
|
gen_helper_hptof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
|
||||||
|
} else {
|
||||||
|
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
|
||||||
|
}
|
||||||
|
break;
|
||||||
case OPC2_32_RR_CMP_F:
|
case OPC2_32_RR_CMP_F:
|
||||||
gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
|
gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
|
||||||
break;
|
break;
|
||||||
@ -6269,8 +6286,15 @@ static void decode_rr_divide(DisasContext *ctx)
|
|||||||
case OPC2_32_RR_ITOF:
|
case OPC2_32_RR_ITOF:
|
||||||
gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
|
gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
|
||||||
break;
|
break;
|
||||||
|
case OPC2_32_RR_FTOU:
|
||||||
|
gen_helper_ftou(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
|
||||||
|
break;
|
||||||
case OPC2_32_RR_FTOUZ:
|
case OPC2_32_RR_FTOUZ:
|
||||||
gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
|
if (has_feature(ctx, TRICORE_FEATURE_131)) {
|
||||||
|
gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
|
||||||
|
} else {
|
||||||
|
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
|
||||||
|
}
|
||||||
break;
|
break;
|
||||||
case OPC2_32_RR_UPDFL:
|
case OPC2_32_RR_UPDFL:
|
||||||
gen_helper_updfl(cpu_env, cpu_gpr_d[r1]);
|
gen_helper_updfl(cpu_env, cpu_gpr_d[r1]);
|
||||||
@ -6554,7 +6578,10 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
|
|||||||
|
|
||||||
break;
|
break;
|
||||||
case OPC2_32_RRPW_INSERT:
|
case OPC2_32_RRPW_INSERT:
|
||||||
if (pos + width <= 32) {
|
/* tcg_gen_deposit_tl() does not handle the case of width = 0 */
|
||||||
|
if (width == 0) {
|
||||||
|
tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
|
||||||
|
} else if (pos + width <= 32) {
|
||||||
tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
|
tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
|
||||||
pos, width);
|
pos, width);
|
||||||
}
|
}
|
||||||
@ -6669,6 +6696,14 @@ static void decode_rrr_divide(DisasContext *ctx)
|
|||||||
gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
|
gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
|
||||||
cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
|
cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
|
||||||
break;
|
break;
|
||||||
|
case OPC2_32_RRR_CRCN:
|
||||||
|
if (has_feature(ctx, TRICORE_FEATURE_162)) {
|
||||||
|
gen_helper_crcn(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2],
|
||||||
|
cpu_gpr_d[r3]);
|
||||||
|
} else {
|
||||||
|
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
|
||||||
|
}
|
||||||
|
break;
|
||||||
case OPC2_32_RRR_ADD_F:
|
case OPC2_32_RRR_ADD_F:
|
||||||
gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
|
gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
|
||||||
break;
|
break;
|
||||||
@ -8192,12 +8227,12 @@ static void decode_32Bit_opc(DisasContext *ctx)
|
|||||||
temp2 = tcg_temp_new(); /* width*/
|
temp2 = tcg_temp_new(); /* width*/
|
||||||
temp3 = tcg_temp_new(); /* pos */
|
temp3 = tcg_temp_new(); /* pos */
|
||||||
|
|
||||||
CHECK_REG_PAIR(r3);
|
CHECK_REG_PAIR(r2);
|
||||||
|
|
||||||
tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
|
tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f);
|
||||||
tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
|
tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f);
|
||||||
|
|
||||||
gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
|
gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3);
|
||||||
break;
|
break;
|
||||||
/* RCRW Format */
|
/* RCRW Format */
|
||||||
case OPCM_32_RCRW_MASK_INSERT:
|
case OPCM_32_RCRW_MASK_INSERT:
|
||||||
@ -8367,7 +8402,7 @@ static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx)
|
|||||||
* 4 bytes from the page boundary, so we cross the page if the first
|
* 4 bytes from the page boundary, so we cross the page if the first
|
||||||
* 16 bits indicate that this is a 32 bit insn.
|
* 16 bits indicate that this is a 32 bit insn.
|
||||||
*/
|
*/
|
||||||
uint16_t insn = cpu_lduw_code(env, ctx->base.pc_next);
|
uint16_t insn = translator_lduw(env, &ctx->base, ctx->base.pc_next);
|
||||||
|
|
||||||
return !tricore_insn_is_16bit(insn);
|
return !tricore_insn_is_16bit(insn);
|
||||||
}
|
}
|
||||||
@ -8380,14 +8415,15 @@ static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
|
|||||||
uint16_t insn_lo;
|
uint16_t insn_lo;
|
||||||
bool is_16bit;
|
bool is_16bit;
|
||||||
|
|
||||||
insn_lo = cpu_lduw_code(env, ctx->base.pc_next);
|
insn_lo = translator_lduw(env, &ctx->base, ctx->base.pc_next);
|
||||||
is_16bit = tricore_insn_is_16bit(insn_lo);
|
is_16bit = tricore_insn_is_16bit(insn_lo);
|
||||||
if (is_16bit) {
|
if (is_16bit) {
|
||||||
ctx->opcode = insn_lo;
|
ctx->opcode = insn_lo;
|
||||||
ctx->pc_succ_insn = ctx->base.pc_next + 2;
|
ctx->pc_succ_insn = ctx->base.pc_next + 2;
|
||||||
decode_16Bit_opc(ctx);
|
decode_16Bit_opc(ctx);
|
||||||
} else {
|
} else {
|
||||||
uint32_t insn_hi = cpu_lduw_code(env, ctx->base.pc_next + 2);
|
uint32_t insn_hi = translator_lduw(env, &ctx->base,
|
||||||
|
ctx->base.pc_next + 2);
|
||||||
ctx->opcode = insn_hi << 16 | insn_lo;
|
ctx->opcode = insn_hi << 16 | insn_lo;
|
||||||
ctx->pc_succ_insn = ctx->base.pc_next + 4;
|
ctx->pc_succ_insn = ctx->base.pc_next + 4;
|
||||||
decode_32Bit_opc(ctx);
|
decode_32Bit_opc(ctx);
|
||||||
|
@ -1152,6 +1152,8 @@ enum {
|
|||||||
OPC2_32_RR_ITOF = 0x14,
|
OPC2_32_RR_ITOF = 0x14,
|
||||||
OPC2_32_RR_CMP_F = 0x00,
|
OPC2_32_RR_CMP_F = 0x00,
|
||||||
OPC2_32_RR_FTOIZ = 0x13,
|
OPC2_32_RR_FTOIZ = 0x13,
|
||||||
|
OPC2_32_RR_FTOHP = 0x25, /* 1.6.2 only */
|
||||||
|
OPC2_32_RR_HPTOF = 0x24, /* 1.6.2 only */
|
||||||
OPC2_32_RR_FTOQ31 = 0x11,
|
OPC2_32_RR_FTOQ31 = 0x11,
|
||||||
OPC2_32_RR_FTOQ31Z = 0x18,
|
OPC2_32_RR_FTOQ31Z = 0x18,
|
||||||
OPC2_32_RR_FTOU = 0x12,
|
OPC2_32_RR_FTOU = 0x12,
|
||||||
@ -1247,6 +1249,7 @@ enum {
|
|||||||
OPC2_32_RRR_SUB_F = 0x03,
|
OPC2_32_RRR_SUB_F = 0x03,
|
||||||
OPC2_32_RRR_MADD_F = 0x06,
|
OPC2_32_RRR_MADD_F = 0x06,
|
||||||
OPC2_32_RRR_MSUB_F = 0x07,
|
OPC2_32_RRR_MSUB_F = 0x07,
|
||||||
|
OPC2_32_RRR_CRCN = 0x01, /* 1.6.2 up */
|
||||||
};
|
};
|
||||||
/*
|
/*
|
||||||
* RRR1 Format
|
* RRR1 Format
|
||||||
|
@ -9,11 +9,15 @@ CFLAGS = -mtc162 -c -I$(TESTS_PATH)
|
|||||||
TESTS += test_abs.asm.tst
|
TESTS += test_abs.asm.tst
|
||||||
TESTS += test_bmerge.asm.tst
|
TESTS += test_bmerge.asm.tst
|
||||||
TESTS += test_clz.asm.tst
|
TESTS += test_clz.asm.tst
|
||||||
|
TESTS += test_crcn.asm.tst
|
||||||
TESTS += test_dextr.asm.tst
|
TESTS += test_dextr.asm.tst
|
||||||
TESTS += test_dvstep.asm.tst
|
TESTS += test_dvstep.asm.tst
|
||||||
TESTS += test_fadd.asm.tst
|
TESTS += test_fadd.asm.tst
|
||||||
TESTS += test_fmul.asm.tst
|
TESTS += test_fmul.asm.tst
|
||||||
|
TESTS += test_ftohp.asm.tst
|
||||||
TESTS += test_ftoi.asm.tst
|
TESTS += test_ftoi.asm.tst
|
||||||
|
TESTS += test_ftou.asm.tst
|
||||||
|
TESTS += test_hptof.asm.tst
|
||||||
TESTS += test_imask.asm.tst
|
TESTS += test_imask.asm.tst
|
||||||
TESTS += test_insert.asm.tst
|
TESTS += test_insert.asm.tst
|
||||||
TESTS += test_ld_bu.asm.tst
|
TESTS += test_ld_bu.asm.tst
|
||||||
@ -25,7 +29,7 @@ TESTS += test_muls.asm.tst
|
|||||||
TESTS += test_boot_to_main.c.tst
|
TESTS += test_boot_to_main.c.tst
|
||||||
TESTS += test_context_save_areas.c.tst
|
TESTS += test_context_save_areas.c.tst
|
||||||
|
|
||||||
QEMU_OPTS += -M tricore_testboard -cpu tc27x -nographic -kernel
|
QEMU_OPTS += -M tricore_testboard -cpu tc37x -nographic -kernel
|
||||||
|
|
||||||
%.pS: $(ASM_TESTS_PATH)/%.S
|
%.pS: $(ASM_TESTS_PATH)/%.S
|
||||||
$(CC) -E -o $@ $<
|
$(CC) -E -o $@ $<
|
||||||
|
@ -12,31 +12,31 @@
|
|||||||
#define TESTDEV_ADDR 0xf0000000
|
#define TESTDEV_ADDR 0xf0000000
|
||||||
/* Register definitions */
|
/* Register definitions */
|
||||||
#define DREG_RS1 %d0
|
#define DREG_RS1 %d0
|
||||||
#define DREG_RS2 %d1
|
#define DREG_RS2 %d2
|
||||||
#define DREG_RS3 %d2
|
#define DREG_RS3 %d4
|
||||||
#define DREG_CALC_RESULT %d3
|
#define DREG_CALC_RESULT %d5
|
||||||
#define DREG_CALC_PSW %d4
|
#define DREG_CALC_PSW %d6
|
||||||
#define DREG_CORRECT_PSW %d5
|
#define DREG_CORRECT_PSW %d7
|
||||||
#define DREG_TEMP_LI %d10
|
#define DREG_TEMP_LI %d13
|
||||||
#define DREG_TEMP %d11
|
#define DREG_TEMP %d14
|
||||||
#define DREG_TEST_NUM %d14
|
#define DREG_TEST_NUM %d8
|
||||||
#define DREG_CORRECT_RESULT %d15
|
#define DREG_CORRECT_RESULT %d9
|
||||||
#define DREG_CORRECT_RESULT_2 %d13
|
#define DREG_CORRECT_RESULT_2 %d10
|
||||||
|
|
||||||
#define AREG_ADDR %a0
|
#define AREG_ADDR %a0
|
||||||
#define AREG_CORRECT_RESULT %a3
|
#define AREG_CORRECT_RESULT %a3
|
||||||
|
|
||||||
#define DREG_DEV_ADDR %a15
|
#define DREG_DEV_ADDR %a15
|
||||||
|
|
||||||
#define EREG_RS1 %e6
|
#define EREG_RS1 %e0
|
||||||
#define EREG_RS1_LO %d6
|
#define EREG_RS1_LO %d0
|
||||||
#define EREG_RS1_HI %d7
|
#define EREG_RS1_HI %d1
|
||||||
#define EREG_RS2 %e8
|
#define EREG_RS2 %e2
|
||||||
#define EREG_RS2_LO %d8
|
#define EREG_RS2_LO %d2
|
||||||
#define EREG_RS2_HI %d9
|
#define EREG_RS2_HI %d3
|
||||||
#define EREG_CALC_RESULT %e8
|
#define EREG_CALC_RESULT %e6
|
||||||
#define EREG_CALC_RESULT_HI %d9
|
#define EREG_CALC_RESULT_LO %d6
|
||||||
#define EREG_CALC_RESULT_LO %d8
|
#define EREG_CALC_RESULT_HI %d7
|
||||||
#define EREG_CORRECT_RESULT_LO %d0
|
#define EREG_CORRECT_RESULT_LO %d0
|
||||||
#define EREG_CORRECT_RESULT_HI %d1
|
#define EREG_CORRECT_RESULT_HI %d1
|
||||||
|
|
||||||
@ -46,7 +46,8 @@ test_ ## num: \
|
|||||||
code; \
|
code; \
|
||||||
LI(DREG_CORRECT_RESULT, correct) \
|
LI(DREG_CORRECT_RESULT, correct) \
|
||||||
mov DREG_TEST_NUM, num; \
|
mov DREG_TEST_NUM, num; \
|
||||||
jne testreg, DREG_CORRECT_RESULT, fail \
|
jne testreg, DREG_CORRECT_RESULT, fail; \
|
||||||
|
mov testreg, 0
|
||||||
|
|
||||||
#define TEST_CASE_E(num, correct_lo, correct_hi, code...) \
|
#define TEST_CASE_E(num, correct_lo, correct_hi, code...) \
|
||||||
test_ ## num: \
|
test_ ## num: \
|
||||||
@ -161,6 +162,30 @@ test_ ## num: \
|
|||||||
insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2; \
|
insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2; \
|
||||||
)
|
)
|
||||||
|
|
||||||
|
#define TEST_D_DDII(insn, num, result, rs1, rs2, imm1, imm2) \
|
||||||
|
TEST_CASE(num, DREG_CALC_RESULT, result, \
|
||||||
|
LI(DREG_RS1, rs1); \
|
||||||
|
LI(DREG_RS2, rs2); \
|
||||||
|
rstv; \
|
||||||
|
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm1, imm2; \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define TEST_D_DIE(insn, num, result, rs1, imm1, rs2_lo, rs2_hi)\
|
||||||
|
TEST_CASE(num, DREG_CALC_RESULT, result, \
|
||||||
|
LI(DREG_RS1, rs1); \
|
||||||
|
LI(EREG_RS2_LO, rs2_lo); \
|
||||||
|
LI(EREG_RS2_HI, rs2_hi); \
|
||||||
|
rstv; \
|
||||||
|
insn DREG_CALC_RESULT, DREG_RS1, imm1, EREG_RS2; \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define TEST_D_DIII(insn, num, result, rs1, imm1, imm2, imm3)\
|
||||||
|
TEST_CASE(num, DREG_CALC_RESULT, result, \
|
||||||
|
LI(DREG_RS1, rs1); \
|
||||||
|
rstv; \
|
||||||
|
insn DREG_CALC_RESULT, DREG_RS1, imm1, imm2, imm3; \
|
||||||
|
)
|
||||||
|
|
||||||
#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
|
#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
|
||||||
TEST_CASE_E(num, res_lo, res_hi, \
|
TEST_CASE_E(num, res_lo, res_hi, \
|
||||||
LI(EREG_RS1_LO, rs1_lo); \
|
LI(EREG_RS1_LO, rs1_lo); \
|
||||||
|
9
tests/tcg/tricore/asm/test_crcn.S
Normal file
9
tests/tcg/tricore/asm/test_crcn.S
Normal file
@ -0,0 +1,9 @@
|
|||||||
|
#include "macros.h"
|
||||||
|
.text
|
||||||
|
.global _start
|
||||||
|
_start:
|
||||||
|
# insn num result rs1 rs2 rs3
|
||||||
|
# | | | | | |
|
||||||
|
TEST_D_DDD(crcn, 1, 0x00002bed, 0x0, 0xa10ddeed, 0x0)
|
||||||
|
|
||||||
|
TEST_PASSFAIL
|
14
tests/tcg/tricore/asm/test_ftohp.S
Normal file
14
tests/tcg/tricore/asm/test_ftohp.S
Normal file
@ -0,0 +1,14 @@
|
|||||||
|
#include "macros.h"
|
||||||
|
.text
|
||||||
|
.global _start
|
||||||
|
_start:
|
||||||
|
TEST_D_D(ftohp, 1, 0xffff, 0xffffffff)
|
||||||
|
TEST_D_D(ftohp, 2, 0xfc00, 0xff800000)
|
||||||
|
TEST_D_D(ftohp, 3, 0x7c00, 0x7f800000)
|
||||||
|
TEST_D_D(ftohp, 4, 0x0, 0x0)
|
||||||
|
TEST_D_D(ftohp, 5, 0x5, 0x34a43580)
|
||||||
|
|
||||||
|
#TEST_D_D_PSW(ftohp, 6, 0x400, 0x8c000b80, 0x387fee74)
|
||||||
|
|
||||||
|
TEST_PASSFAIL
|
||||||
|
|
12
tests/tcg/tricore/asm/test_ftou.S
Normal file
12
tests/tcg/tricore/asm/test_ftou.S
Normal file
@ -0,0 +1,12 @@
|
|||||||
|
#include "macros.h"
|
||||||
|
.text
|
||||||
|
.global _start
|
||||||
|
_start:
|
||||||
|
TEST_D_D(ftou, 1, 0x00000000, 0x1733f6c2)
|
||||||
|
TEST_D_D(ftou, 2, 0x00000000, 0x2c9d9cdc)
|
||||||
|
TEST_D_D(ftou, 3, 0xffffffff, 0x56eb7395)
|
||||||
|
TEST_D_D(ftou, 4, 0x79900800, 0x4ef32010)
|
||||||
|
TEST_D_D(ftou, 5, 0x0353f510, 0x4c54fd44)
|
||||||
|
|
||||||
|
TEST_PASSFAIL
|
||||||
|
|
12
tests/tcg/tricore/asm/test_hptof.S
Normal file
12
tests/tcg/tricore/asm/test_hptof.S
Normal file
@ -0,0 +1,12 @@
|
|||||||
|
#include "macros.h"
|
||||||
|
.text
|
||||||
|
.global _start
|
||||||
|
_start:
|
||||||
|
TEST_D_D(hptof, 1, 0xba190000, 0xcc0e90c8)
|
||||||
|
TEST_D_D(hptof, 2, 0x3eaea000, 0x8be23575)
|
||||||
|
TEST_D_D(hptof, 3, 0xc33b8000, 0xcc48d9dc)
|
||||||
|
TEST_D_D(hptof, 4, 0x43e2a000, 0xaef95f15)
|
||||||
|
TEST_D_D(hptof, 5, 0x3d55e000, 0x04932aaf)
|
||||||
|
|
||||||
|
TEST_PASSFAIL
|
||||||
|
|
@ -6,4 +6,18 @@ _start:
|
|||||||
# | | | | | | |
|
# | | | | | | |
|
||||||
TEST_D_DIDI(insert, 1, 0x7fffffff, 0xffffffff, 0xa, 0x10, 0x8)
|
TEST_D_DIDI(insert, 1, 0x7fffffff, 0xffffffff, 0xa, 0x10, 0x8)
|
||||||
|
|
||||||
|
# insn num result rs1 imm1 imm2 imm3
|
||||||
|
# | | | | | | |
|
||||||
|
TEST_D_DIII(insert, 2, 0xd38fe370, 0xd38fe370, 0x4, 0x4 , 0x0)
|
||||||
|
TEST_D_DIII(insert, 3, 0xd38fe374, 0xd38fe370, 0x4, 0x0 , 0x4)
|
||||||
|
|
||||||
|
# insn num result rs1 rs2 pos width
|
||||||
|
# | | | | | | |
|
||||||
|
TEST_D_DDII(insert, 4, 0x03c1e53c, 0x03c1e53c, 0x45821385, 0x7 ,0x0)
|
||||||
|
|
||||||
|
# insn num result rs1 imm1 rs2_h rs2_l
|
||||||
|
# | | | | | | |
|
||||||
|
TEST_D_DIE(insert, 5, 0xe30c308d, 0xe30c308d ,0x3 , 0x00000000 ,0x00000000)
|
||||||
|
TEST_D_DIE(insert, 6, 0x669b0120, 0x669b2820 ,0x2 , 0x5530a1c7 ,0x3a2b0f67)
|
||||||
|
|
||||||
TEST_PASSFAIL
|
TEST_PASSFAIL
|
||||||
|
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Reference in New Issue
Block a user