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ppc patch queue for qemu-2.5 20151130

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target-ppc and related bugfix patches for qemu-2.5
 
 I don't have the facilities to test the Macintosh and BookE related
 patches.  I've sanity checked them (inspection + make check), but I'm
 otherwise relying on the submitters.
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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.5-20151130' into staging

ppc patch queue for qemu-2.5 20151130

target-ppc and related bugfix patches for qemu-2.5

I don't have the facilities to test the Macintosh and BookE related
patches.  I've sanity checked them (inspection + make check), but I'm
otherwise relying on the submitters.

# gpg: Signature made Mon 30 Nov 2015 08:42:01 GMT using RSA key ID 20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>"
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>"
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.5-20151130:
  target-ppc/fpu_helper: fix FPSCR_FX bit shift operation
  target-ppc: Move the FPSCR bit update macros to cpu.h
  hw/ppc/ppc405_boards: Fix infinite recursion by converting taihu_cpld from old_mmio
  hw/ppc/spapr: Remove duplicated "pseries" alias
  mac_dbdma: always initialize channel field in DBDMA_channel

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2015-11-30 17:09:35 +00:00
commit a2485925f7
6 changed files with 41 additions and 79 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/misc/macio/mac_dbdma.c
View File

@ -557,7 +557,6 @@ void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
DBDMA_DPRINTF("DBDMA_register_channel 0x%x\n", nchan);
ch->irq = irq;
ch->channel = nchan;
ch->rw = rw;
ch->flush = flush;
ch->io.opaque = opaque;
@ -753,6 +752,7 @@ void* DBDMA_init (MemoryRegion **dbdma_mem)
for (i = 0; i < DBDMA_CHANNELS; i++) {
DBDMA_io *io = &s->channels[i].io;
qemu_iovec_init(&io->iov, 1);
s->channels[i].channel = i;
}
memory_region_init_io(&s->mem, NULL, &dbdma_ops, s, "dbdma", 0x1000);

52
hw/ppc/ppc405_boards.c
View File

@ -408,7 +408,7 @@ struct taihu_cpld_t {
uint8_t reg1;
};
static uint32_t taihu_cpld_readb (void *opaque, hwaddr addr)
static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size)
{
taihu_cpld_t *cpld;
uint32_t ret;
@ -429,8 +429,8 @@ static uint32_t taihu_cpld_readb (void *opaque, hwaddr addr)
return ret;
}
static void taihu_cpld_writeb (void *opaque,
hwaddr addr, uint32_t value)
static void taihu_cpld_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
taihu_cpld_t *cpld;
@ -447,48 +447,12 @@ static void taihu_cpld_writeb (void *opaque,
}
}
static uint32_t taihu_cpld_readw (void *opaque, hwaddr addr)
{
uint32_t ret;
ret = taihu_cpld_readb(opaque, addr) << 8;
ret |= taihu_cpld_readb(opaque, addr + 1);
return ret;
}
static void taihu_cpld_writew (void *opaque,
hwaddr addr, uint32_t value)
{
taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
}
static uint32_t taihu_cpld_readl (void *opaque, hwaddr addr)
{
uint32_t ret;
ret = taihu_cpld_readb(opaque, addr) << 24;
ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
ret |= taihu_cpld_readb(opaque, addr + 3);
return ret;
}
static void taihu_cpld_writel (void *opaque,
hwaddr addr, uint32_t value)
{
taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
}
static const MemoryRegionOps taihu_cpld_ops = {
.old_mmio = {
.read = { taihu_cpld_readb, taihu_cpld_readw, taihu_cpld_readl, },
.write = { taihu_cpld_writeb, taihu_cpld_writew, taihu_cpld_writel, },
.read = taihu_cpld_read,
.write = taihu_cpld_write,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
},
.endianness = DEVICE_NATIVE_ENDIAN,
};

2
hw/ppc/spapr.c
View File

@ -2423,8 +2423,6 @@ static void spapr_machine_2_4_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "pSeries Logical Partition (PAPR compliant) v2.4";
mc->alias = "pseries";
mc->is_default = 0;
mc->compat_props = compat_props;
}

21
target-ppc/cpu.h
View File

@ -684,6 +684,27 @@ enum {
#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
0x1F)
#define FP_FX (1ull << FPSCR_FX)
#define FP_FEX (1ull << FPSCR_FEX)
#define FP_OX (1ull << FPSCR_OX)
#define FP_OE (1ull << FPSCR_OE)
#define FP_UX (1ull << FPSCR_UX)
#define FP_UE (1ull << FPSCR_UE)
#define FP_XX (1ull << FPSCR_XX)
#define FP_XE (1ull << FPSCR_XE)
#define FP_ZX (1ull << FPSCR_ZX)
#define FP_ZE (1ull << FPSCR_ZE)
#define FP_VX (1ull << FPSCR_VX)
#define FP_VXSNAN (1ull << FPSCR_VXSNAN)
#define FP_VXISI (1ull << FPSCR_VXISI)
#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
#define FP_VXIDI (1ull << FPSCR_VXIDI)
#define FP_VXVC (1ull << FPSCR_VXVC)
#define FP_VXCVI (1ull << FPSCR_VXCVI)
#define FP_VE (1ull << FPSCR_VE)
#define FP_FI (1ull << FPSCR_FI)
/*****************************************************************************/
/* Vector status and control register */
#define VSCR_NJ 16 /* Vector non-java */

21
target-ppc/dfp_helper.c
View File

@ -170,27 +170,6 @@ static void dfp_prepare_decimal128(struct PPC_DFP *dfp, uint64_t *a,
}
}
#define FP_FX (1ull << FPSCR_FX)
#define FP_FEX (1ull << FPSCR_FEX)
#define FP_OX (1ull << FPSCR_OX)
#define FP_OE (1ull << FPSCR_OE)
#define FP_UX (1ull << FPSCR_UX)
#define FP_UE (1ull << FPSCR_UE)
#define FP_XX (1ull << FPSCR_XX)
#define FP_XE (1ull << FPSCR_XE)
#define FP_ZX (1ull << FPSCR_ZX)
#define FP_ZE (1ull << FPSCR_ZE)
#define FP_VX (1ull << FPSCR_VX)
#define FP_VXSNAN (1ull << FPSCR_VXSNAN)
#define FP_VXISI (1ull << FPSCR_VXISI)
#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
#define FP_VXIDI (1ull << FPSCR_VXIDI)
#define FP_VXVC (1ull << FPSCR_VXVC)
#define FP_VXCVI (1ull << FPSCR_VXCVI)
#define FP_VE (1ull << FPSCR_VE)
#define FP_FI (1ull << FPSCR_FI)
static void dfp_set_FPSCR_flag(struct PPC_DFP *dfp, uint64_t flag,
uint64_t enabled)
{

22
target-ppc/fpu_helper.c
View File

@ -194,7 +194,7 @@ static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op,
/* Update the floating-point invalid operation summary */
env->fpscr |= 1 << FPSCR_VX;
/* Update the floating-point exception summary */
env->fpscr |= 1 << FPSCR_FX;
env->fpscr |= FP_FX;
if (ve != 0) {
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
@ -211,7 +211,7 @@ static inline void float_zero_divide_excp(CPUPPCState *env)
env->fpscr |= 1 << FPSCR_ZX;
env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
/* Update the floating-point exception summary */
env->fpscr |= 1 << FPSCR_FX;
env->fpscr |= FP_FX;
if (fpscr_ze != 0) {
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
@ -228,7 +228,7 @@ static inline void float_overflow_excp(CPUPPCState *env)
env->fpscr |= 1 << FPSCR_OX;
/* Update the floating-point exception summary */
env->fpscr |= 1 << FPSCR_FX;
env->fpscr |= FP_FX;
if (fpscr_oe != 0) {
/* XXX: should adjust the result */
/* Update the floating-point enabled exception summary */
@ -248,7 +248,7 @@ static inline void float_underflow_excp(CPUPPCState *env)
env->fpscr |= 1 << FPSCR_UX;
/* Update the floating-point exception summary */
env->fpscr |= 1 << FPSCR_FX;
env->fpscr |= FP_FX;
if (fpscr_ue != 0) {
/* XXX: should adjust the result */
/* Update the floating-point enabled exception summary */
@ -265,7 +265,7 @@ static inline void float_inexact_excp(CPUPPCState *env)
env->fpscr |= 1 << FPSCR_XX;
/* Update the floating-point exception summary */
env->fpscr |= 1 << FPSCR_FX;
env->fpscr |= FP_FX;
if (fpscr_xe != 0) {
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
@ -330,31 +330,31 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
if (prev == 0) {
switch (bit) {
case FPSCR_VX:
env->fpscr |= 1 << FPSCR_FX;
env->fpscr |= FP_FX;
if (fpscr_ve) {
goto raise_ve;
}
break;
case FPSCR_OX:
env->fpscr |= 1 << FPSCR_FX;
env->fpscr |= FP_FX;
if (fpscr_oe) {
goto raise_oe;
}
break;
case FPSCR_UX:
env->fpscr |= 1 << FPSCR_FX;
env->fpscr |= FP_FX;
if (fpscr_ue) {
goto raise_ue;
}
break;
case FPSCR_ZX:
env->fpscr |= 1 << FPSCR_FX;
env->fpscr |= FP_FX;
if (fpscr_ze) {
goto raise_ze;
}
break;
case FPSCR_XX:
env->fpscr |= 1 << FPSCR_FX;
env->fpscr |= FP_FX;
if (fpscr_xe) {
goto raise_xe;
}
@ -369,7 +369,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
case FPSCR_VXSQRT:
case FPSCR_VXCVI:
env->fpscr |= 1 << FPSCR_VX;
env->fpscr |= 1 << FPSCR_FX;
env->fpscr |= FP_FX;
if (fpscr_ve != 0) {
goto raise_ve;
}