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riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead

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Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...)
in various sifive models.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Bin Meng 2019-09-06 09:19:54 -07:00 committed by Palmer Dabbelt
parent 9f79638ec5
commit a2360c854f
No known key found for this signature in database
GPG Key ID: EF4CA1502CCBAB41
3 changed files with 13 additions and 9 deletions
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8
hw/riscv/sifive_prci.c
View File

@ -20,6 +20,7 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
#include "qemu/log.h"
#include "qemu/module.h" #include "qemu/module.h"
#include "target/riscv/cpu.h" #include "target/riscv/cpu.h"
#include "hw/hw.h" #include "hw/hw.h"
@ -38,7 +39,8 @@ static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
case SIFIVE_PRCI_PLLOUTDIV: case SIFIVE_PRCI_PLLOUTDIV:
return s->plloutdiv; return s->plloutdiv;
} }
hw_error("%s: read: addr=0x%x\n", __func__, (int)addr); qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n",
__func__, (int)addr);
return 0; return 0;
} }
@ -66,8 +68,8 @@ static void sifive_prci_write(void *opaque, hwaddr addr,
s->plloutdiv = (uint32_t) val64; s->plloutdiv = (uint32_t) val64;
break; break;
default: default:
hw_error("%s: bad write: addr=0x%x v=0x%x\n", qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n",
__func__, (int)addr, (int)val64); __func__, (int)addr, (int)val64);
} }
} }

5
hw/riscv/sifive_test.c
View File

@ -20,6 +20,7 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
#include "qemu/log.h"
#include "qemu/module.h" #include "qemu/module.h"
#include "sysemu/runstate.h" #include "sysemu/runstate.h"
#include "target/riscv/cpu.h" #include "target/riscv/cpu.h"
@ -49,8 +50,8 @@ static void sifive_test_write(void *opaque, hwaddr addr,
break; break;
} }
} }
hw_error("%s: write: addr=0x%x val=0x%016" PRIx64 "\n", qemu_log_mask(LOG_GUEST_ERROR, "%s: write: addr=0x%x val=0x%016" PRIx64 "\n",
__func__, (int)addr, val64); __func__, (int)addr, val64);
} }
static const MemoryRegionOps sifive_test_ops = { static const MemoryRegionOps sifive_test_ops = {

9
hw/riscv/sifive_uart.c
View File

@ -18,6 +18,7 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu/log.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
#include "chardev/char.h" #include "chardev/char.h"
#include "chardev/char-fe.h" #include "chardev/char-fe.h"
@ -95,8 +96,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
return s->div; return s->div;
} }
hw_error("%s: bad read: addr=0x%x\n", qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n",
__func__, (int)addr); __func__, (int)addr);
return 0; return 0;
} }
@ -127,8 +128,8 @@ uart_write(void *opaque, hwaddr addr,
s->div = val64; s->div = val64;
return; return;
} }
hw_error("%s: bad write: addr=0x%x v=0x%x\n", qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n",
__func__, (int)addr, (int)value); __func__, (int)addr, (int)value);
} }
static const MemoryRegionOps uart_ops = { static const MemoryRegionOps uart_ops = {