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target-s390x: implement LAY and LAEY instructions

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This complete the general-instructions-extension facility, enable it.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
[agraf: remove facility bit]
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Aurelien Jarno 2015-05-25 01:47:31 +02:00 committed by Alexander Graf
parent 92892330e7
commit a1c7610a68
2 changed files with 38 additions and 0 deletions
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3
target-s390x/insn-data.def
View File

@ -357,6 +357,9 @@
/* LOAD ADDRESS */
C(0x4100, LA, RX_a, Z, 0, a2, 0, r1, mov2, 0)
C(0xe371, LAY, RXY_a, LD, 0, a2, 0, r1, mov2, 0)
/* LOAD ADDRESS EXTENDED */
C(0x5100, LAE, RX_a, Z, 0, a2, 0, r1, mov2e, 0)
C(0xe375, LAEY, RXY_a, GIE, 0, a2, 0, r1, mov2e, 0)
/* LOAD ADDRESS RELATIVE LONG */
C(0xc000, LARL, RIL_b, Z, 0, ri2, 0, r1, mov2, 0)
/* LOAD AND ADD */

35
target-s390x/translate.c
View File

@ -2596,6 +2596,41 @@ static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
return NO_EXIT;
}
static ExitStatus op_mov2e(DisasContext *s, DisasOps *o)
{
int b2 = get_field(s->fields, b2);
TCGv ar1 = tcg_temp_new_i64();
o->out = o->in2;
o->g_out = o->g_in2;
TCGV_UNUSED_I64(o->in2);
o->g_in2 = false;
switch (s->tb->flags & FLAG_MASK_ASC) {
case PSW_ASC_PRIMARY >> 32:
tcg_gen_movi_i64(ar1, 0);
break;
case PSW_ASC_ACCREG >> 32:
tcg_gen_movi_i64(ar1, 1);
break;
case PSW_ASC_SECONDARY >> 32:
if (b2) {
tcg_gen_ld32u_i64(ar1, cpu_env, offsetof(CPUS390XState, aregs[b2]));
} else {
tcg_gen_movi_i64(ar1, 0);
}
break;
case PSW_ASC_HOME >> 32:
tcg_gen_movi_i64(ar1, 2);
break;
}
tcg_gen_st32_i64(ar1, cpu_env, offsetof(CPUS390XState, aregs[1]));
tcg_temp_free_i64(ar1);
return NO_EXIT;
}
static ExitStatus op_movx(DisasContext *s, DisasOps *o)
{
o->out = o->in1;