From 2658594ff64828bf4230d9224b394034dae14028 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 11 Jul 2019 14:52:46 +0200 Subject: [PATCH 1/2] hw/block/pflash_cfi02: Explicit switch fallthrough for ERASE commands MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Previous to commit ddb6f2254, the DQ2 bit was incorrectly set during PROGRAM command (0xA0). The commit reordered the switch cases to only set the DQ2 bit for the ERASE commands using a fallthrough, but did not explicit the fallthrough is intentional. Mark the switch fallthrough with a comment interpretable by C preprocessors and static analysis tools. Reported-by: Coverity (CID 1403012) Reviewed-by: Peter Maydell Message-Id: <20190711130759.27720-1-philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi02.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 83084b9d72..f68837a449 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -367,6 +367,7 @@ static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width) case 0x30: /* Sector Erase */ /* Toggle bit 2 during erase, but not program. */ toggle_dq2(pfl); + /* fall through */ case 0xA0: /* Program */ /* Toggle bit 6 */ toggle_dq6(pfl); From 611c749c3b86fe377c94ea301feab3d9ce3bf617 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 16 Jul 2019 17:49:55 +0200 Subject: [PATCH 2/2] hw/block/pflash_cfi01: Start state machine as READY to accept commands MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the state machine is ready to accept command, the bit 7 of the status register (SR) is set to 1. The guest polls the status register and check this bit before writting command to the internal 'Write State Machine' (WSM). Set SR.7 bit to 1 when the device is created. There is no migration impact by this change. Reference: Read Array Flowchart "Common Flash Interface (CFI) and Command Sets" (Intel Application Note 646) Appendix B "Basic Command Set" Reviewed-by: John Snow Reviewed-by: Alistair Francis Regression-tested-by: Laszlo Ersek Message-Id: <20190715121338.20600-5-philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index db4a246b22..435be1e35c 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -777,7 +777,7 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) pfl->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pflash_timer, pfl); pfl->wcycle = 0; pfl->cmd = 0; - pfl->status = 0; + pfl->status = 0x80; /* WSM ready */ /* Hardcoded CFI table */ /* Standard "QRY" string */ pfl->cfi_table[0x10] = 'Q';