i386: Add missing cpu feature bits in EPYC model
Adds the following missing CPUID bits: perfctr-core : core performance counter extensions support. Enables the VM to use extended performance counter support. It enables six programmable counters instead of 4 counters. clzero : instruction zeroes out the 64 byte cache line specified in RAX. xsaveerptr : XSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES always save error pointers and FXRSTOR, XRSTOR, XRSTORS always restore error pointers. ibpb : Indirect Branch Prediction Barrie. xsaves : XSAVES, XRSTORS and IA32_XSS supported. Depends on following kernel commits: 40bc47b08b6e ("kvm: x86: Enumerate support for CLZERO instruction") 504ce1954fba ("KVM: x86: Expose XSAVEERPTR to the guest") 52297436199d ("kvm: svm: Update svm_xsaves_supported") These new features will be added in EPYC-v3. The -cpu help output after the change. x86 EPYC-v1 AMD EPYC Processor x86 EPYC-v2 AMD EPYC Processor (with IBPB) x86 EPYC-v3 AMD EPYC Processor Signed-off-by: Babu Moger <babu.moger@amd.com> Message-Id: <157314965662.23828.3063243729449408327.stgit@naples-babu.amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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@ -3942,10 +3942,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
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CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
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CPUID_7_0_EBX_SHA_NI,
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/* Missing: XSAVES (not supported by some Linux versions,
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* including v4.1 to v4.12).
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* KVM doesn't yet expose any XSAVES state save component.
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*/
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.features[FEAT_XSAVE] =
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CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
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CPUID_XSAVE_XGETBV1,
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@ -3968,6 +3964,19 @@ static X86CPUDefinition builtin_x86_defs[] = {
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{ /* end of list */ }
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}
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},
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{
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.version = 3,
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.props = (PropValue[]) {
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{ "ibpb", "on" },
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{ "perfctr-core", "on" },
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{ "clzero", "on" },
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{ "xsaveerptr", "on" },
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{ "xsaves", "on" },
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{ "model-id",
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"AMD EPYC Processor" },
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{ /* end of list */ }
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}
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},
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{ /* end of list */ }
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}
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},
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