target-sparc: implement sun4v RTC

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
This commit is contained in:
Artyom Tarasenko 2016-03-02 15:26:08 +01:00
parent 3390537b5d
commit a0e893039c
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GPG Key ID: 3360C3F7411A125F
4 changed files with 111 additions and 0 deletions

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@ -1098,6 +1098,12 @@ F: hw/nvram/chrp_nvram.c
F: include/hw/nvram/chrp_nvram.h
F: tests/prom-env-test.c
sun4v RTC
M: Artyom Tarasenko <atar4qemu@gmail.com>
S: Maintained
F: hw/timer/sun4v-rtc.c
F: include/hw/timer/sun4v-rtc.h
Subsystems
----------
Audio

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@ -34,3 +34,5 @@ obj-$(CONFIG_ALLWINNER_A10_PIT) += allwinner-a10-pit.o
common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o

102
hw/timer/sun4v-rtc.c Normal file
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@ -0,0 +1,102 @@
/*
* QEMU sun4v Real Time Clock device
*
* The sun4v_rtc device (sun4v tod clock)
*
* Copyright (c) 2016 Artyom Tarasenko
*
* This code is licensed under the GNU GPL v3 or (at your option) any later
* version.
*/
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "hw/timer/sun4v-rtc.h"
//#define DEBUG_SUN4V_RTC
#ifdef DEBUG_SUN4V_RTC
#define DPRINTF(fmt, ...) \
do { printf("sun4v_rtc: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...) do {} while (0)
#endif
#define TYPE_SUN4V_RTC "sun4v_rtc"
#define SUN4V_RTC(obj) OBJECT_CHECK(Sun4vRtc, (obj), TYPE_SUN4V_RTC)
typedef struct Sun4vRtc {
SysBusDevice parent_obj;
MemoryRegion iomem;
} Sun4vRtc;
static uint64_t sun4v_rtc_read(void *opaque, hwaddr addr,
unsigned size)
{
uint64_t val = qemu_clock_get_ms(QEMU_CLOCK_REALTIME) / 1000;
if (!(addr & 4ULL)) {
/* accessing the high 32 bits */
val >>= 32;
}
DPRINTF("read from " TARGET_FMT_plx " val %lx\n", addr, val);
return val;
}
static void sun4v_rtc_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
DPRINTF("write 0x%x to " TARGET_FMT_plx "\n", (unsigned)val, addr);
}
static const MemoryRegionOps sun4v_rtc_ops = {
.read = sun4v_rtc_read,
.write = sun4v_rtc_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
void sun4v_rtc_init(hwaddr addr)
{
DeviceState *dev;
SysBusDevice *s;
dev = qdev_create(NULL, TYPE_SUN4V_RTC);
s = SYS_BUS_DEVICE(dev);
qdev_init_nofail(dev);
sysbus_mmio_map(s, 0, addr);
}
static int sun4v_rtc_init1(SysBusDevice *dev)
{
Sun4vRtc *s = SUN4V_RTC(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &sun4v_rtc_ops, s,
"sun4v-rtc", 0x08ULL);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
static void sun4v_rtc_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = sun4v_rtc_init1;
}
static const TypeInfo sun4v_rtc_info = {
.name = TYPE_SUN4V_RTC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Sun4vRtc),
.class_init = sun4v_rtc_class_init,
};
static void sun4v_rtc_register_types(void)
{
type_register_static(&sun4v_rtc_info);
}
type_init(sun4v_rtc_register_types)

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@ -0,0 +1 @@
void sun4v_rtc_init(hwaddr addr);