TriCore BOL, BRC, BRN, BRR, RC, RCPW, RCRR, RCR, RLC and RCR insn added
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCgAGBQJUiCzWAAoJEArSxjlracoUDIQP/Awha2fGedZgHy+ih24+75Kz tJDG/EMjDkm/AnP+Emtqst33uvY3nFVgM0UNiJr2LK95IjZIjkS9XW6DhvH1c2Ua 5vtAUC8zssxobQq961HgYCqiaO4v4xnW+moVqYmSt2M7OAbwtXO2fvpssPL2hZJg mVpnn5yAvZeRmIclOaY69Yw9ubgr2TdnO2YldVtMjFZ4P8jbAJDVbFjAG5WSOhJo WwvPszdwTyPxWzgS5ajMBJYVxecJ3lOo3QVfNguYNohPLeViAY4P85dYIl9LS5cP 9uyvzYGr4U6Fsn60uv1HZCm2NXPOvrfByiHUlipI0RKDf70IyDHJebAIWCUd9+cD 0j8ynk7BbY20cgjAfuCZJcMaVWbXaaKLQZPoPUVuTrxR5BZIgC5WPkpE520TUisz wiF5XQa1SYPn1Y42lqLrycmp5adN0YICRSwPtRrMoHfiy0h4GdToNzfMeqjjxYf0 wpOi/gjWjD2lQnAdcorYq54MCV9JabyGT6SnRxBW1ZpU6rDemBJtpfFXFuOdHNCZ oUfoMAB5nmBJAhceSyFaSWhoiTrSXA6K8ya3HaKadjRODpQ1zXl8y0KaJ/IlhmMN CsXFE00f6DDxtdlTIgPgK54sqblX4PPZxEn6Fn+aG6j7wPlOvQguSEcXfi/thR2r wzGcI5/GXE12TKv+ZpQ9 =E4CC -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20141210' into staging TriCore BOL, BRC, BRN, BRR, RC, RCPW, RCRR, RCR, RLC and RCR insn added # gpg: Signature made Wed 10 Dec 2014 11:21:58 GMT using RSA key ID 6B69CA14 # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" * remotes/bkoppelmann/tags/pull-tricore-20141210: target-tricore: Add instructions of RCR opcode format target-tricore: Add instructions of RLC opcode format target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format target-tricore: Make TRICORE_FEATURES implying others. target-tricore: Add instructions of RC opcode format target-tricore: Add instructions of BRR opcode format target-tricore: Add instructions of BRN opcode format target-tricore: Add instructions of BRC opcode format target-tricore: Add instructions of BOL opcode format Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
a09f2d16f6
@ -63,8 +63,17 @@ static bool tricore_cpu_has_work(CPUState *cs)
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static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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TriCoreCPU *cpu = TRICORE_CPU(dev);
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TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(dev);
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CPUTriCoreState *env = &cpu->env;
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/* Some features automatically imply others */
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if (tricore_feature(env, TRICORE_FEATURE_16)) {
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set_feature(env, TRICORE_FEATURE_131);
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}
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if (tricore_feature(env, TRICORE_FEATURE_131)) {
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set_feature(env, TRICORE_FEATURE_13);
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}
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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124
target-tricore/csfr.def
Normal file
124
target-tricore/csfr.def
Normal file
@ -0,0 +1,124 @@
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/* A(ll) access permited
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R(ead only) access
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E(nd init protected) access
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A|R|E(offset, register, feature introducing reg)
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NOTE: PSW is handled as a special case in gen_mtcr/mfcr */
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A(0xfe00, PCXI, TRICORE_FEATURE_13)
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A(0xfe08, PC, TRICORE_FEATURE_13)
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A(0xfe14, SYSCON, TRICORE_FEATURE_13)
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R(0xfe18, CPU_ID, TRICORE_FEATURE_13)
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E(0xfe20, BIV, TRICORE_FEATURE_13)
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E(0xfe24, BTV, TRICORE_FEATURE_13)
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E(0xfe28, ISP, TRICORE_FEATURE_13)
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A(0xfe2c, ICR, TRICORE_FEATURE_13)
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A(0xfe38, FCX, TRICORE_FEATURE_13)
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A(0xfe3c, LCX, TRICORE_FEATURE_13)
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E(0x9400, COMPAT, TRICORE_FEATURE_131)
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/* memory protection register */
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A(0xC000, DPR0_0L, TRICORE_FEATURE_13)
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A(0xC004, DPR0_0U, TRICORE_FEATURE_13)
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A(0xC008, DPR0_1L, TRICORE_FEATURE_13)
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A(0xC00C, DPR0_1U, TRICORE_FEATURE_13)
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A(0xC010, DPR0_2L, TRICORE_FEATURE_13)
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A(0xC014, DPR0_2U, TRICORE_FEATURE_13)
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A(0xC018, DPR0_3L, TRICORE_FEATURE_13)
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A(0xC01C, DPR0_3U, TRICORE_FEATURE_13)
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A(0xC400, DPR1_0L, TRICORE_FEATURE_13)
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A(0xC404, DPR1_0U, TRICORE_FEATURE_13)
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A(0xC408, DPR1_1L, TRICORE_FEATURE_13)
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A(0xC40C, DPR1_1U, TRICORE_FEATURE_13)
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A(0xC410, DPR1_2L, TRICORE_FEATURE_13)
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A(0xC414, DPR1_2U, TRICORE_FEATURE_13)
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A(0xC418, DPR1_3L, TRICORE_FEATURE_13)
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A(0xC41C, DPR1_3U, TRICORE_FEATURE_13)
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A(0xC800, DPR2_0L, TRICORE_FEATURE_13)
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A(0xC804, DPR2_0U, TRICORE_FEATURE_13)
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A(0xC808, DPR2_1L, TRICORE_FEATURE_13)
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A(0xC80C, DPR2_1U, TRICORE_FEATURE_13)
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A(0xC810, DPR2_2L, TRICORE_FEATURE_13)
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A(0xC814, DPR2_2U, TRICORE_FEATURE_13)
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A(0xC818, DPR2_3L, TRICORE_FEATURE_13)
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A(0xC81C, DPR2_3U, TRICORE_FEATURE_13)
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A(0xCC00, DPR3_0L, TRICORE_FEATURE_13)
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A(0xCC04, DPR3_0U, TRICORE_FEATURE_13)
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A(0xCC08, DPR3_1L, TRICORE_FEATURE_13)
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A(0xCC0C, DPR3_1U, TRICORE_FEATURE_13)
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A(0xCC10, DPR3_2L, TRICORE_FEATURE_13)
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A(0xCC14, DPR3_2U, TRICORE_FEATURE_13)
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A(0xCC18, DPR3_3L, TRICORE_FEATURE_13)
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A(0xCC1C, DPR3_3U, TRICORE_FEATURE_13)
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A(0xD000, CPR0_0L, TRICORE_FEATURE_13)
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A(0xD004, CPR0_0U, TRICORE_FEATURE_13)
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A(0xD008, CPR0_1L, TRICORE_FEATURE_13)
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A(0xD00C, CPR0_1U, TRICORE_FEATURE_13)
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A(0xD010, CPR0_2L, TRICORE_FEATURE_13)
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A(0xD014, CPR0_2U, TRICORE_FEATURE_13)
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A(0xD018, CPR0_3L, TRICORE_FEATURE_13)
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A(0xD01C, CPR0_3U, TRICORE_FEATURE_13)
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A(0xD400, CPR1_0L, TRICORE_FEATURE_13)
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A(0xD404, CPR1_0U, TRICORE_FEATURE_13)
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A(0xD408, CPR1_1L, TRICORE_FEATURE_13)
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A(0xD40C, CPR1_1U, TRICORE_FEATURE_13)
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A(0xD410, CPR1_2L, TRICORE_FEATURE_13)
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A(0xD414, CPR1_2U, TRICORE_FEATURE_13)
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A(0xD418, CPR1_3L, TRICORE_FEATURE_13)
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A(0xD41C, CPR1_3U, TRICORE_FEATURE_13)
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A(0xD800, CPR2_0L, TRICORE_FEATURE_13)
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A(0xD804, CPR2_0U, TRICORE_FEATURE_13)
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A(0xD808, CPR2_1L, TRICORE_FEATURE_13)
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A(0xD80C, CPR2_1U, TRICORE_FEATURE_13)
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A(0xD810, CPR2_2L, TRICORE_FEATURE_13)
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A(0xD814, CPR2_2U, TRICORE_FEATURE_13)
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A(0xD818, CPR2_3L, TRICORE_FEATURE_13)
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A(0xD81C, CPR2_3U, TRICORE_FEATURE_13)
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A(0xDC00, CPR3_0L, TRICORE_FEATURE_13)
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A(0xDC04, CPR3_0U, TRICORE_FEATURE_13)
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A(0xDC08, CPR3_1L, TRICORE_FEATURE_13)
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A(0xDC0C, CPR3_1U, TRICORE_FEATURE_13)
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A(0xDC10, CPR3_2L, TRICORE_FEATURE_13)
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A(0xDC14, CPR3_2U, TRICORE_FEATURE_13)
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A(0xDC18, CPR3_3L, TRICORE_FEATURE_13)
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A(0xDC1C, CPR3_3U, TRICORE_FEATURE_13)
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A(0xE000, DPM0, TRICORE_FEATURE_13)
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A(0xE080, DPM1, TRICORE_FEATURE_13)
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A(0xE100, DPM2, TRICORE_FEATURE_13)
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A(0xE180, DPM3, TRICORE_FEATURE_13)
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A(0xE200, CPM0, TRICORE_FEATURE_13)
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A(0xE280, CPM1, TRICORE_FEATURE_13)
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A(0xE300, CPM2, TRICORE_FEATURE_13)
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A(0xE380, CPM3, TRICORE_FEATURE_13)
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/* memory Managment Registers */
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A(0x8000, MMU_CON, TRICORE_FEATURE_13)
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A(0x8004, MMU_ASI, TRICORE_FEATURE_13)
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A(0x800C, MMU_TVA, TRICORE_FEATURE_13)
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A(0x8010, MMU_TPA, TRICORE_FEATURE_13)
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A(0x8014, MMU_TPX, TRICORE_FEATURE_13)
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A(0x8018, MMU_TFA, TRICORE_FEATURE_13)
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E(0x9004, BMACON, TRICORE_FEATURE_131)
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E(0x900C, SMACON, TRICORE_FEATURE_131)
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A(0x9020, DIEAR, TRICORE_FEATURE_131)
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A(0x9024, DIETR, TRICORE_FEATURE_131)
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A(0x9028, CCDIER, TRICORE_FEATURE_131)
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E(0x9044, MIECON, TRICORE_FEATURE_131)
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A(0x9210, PIEAR, TRICORE_FEATURE_131)
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A(0x9214, PIETR, TRICORE_FEATURE_131)
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A(0x9218, CCPIER, TRICORE_FEATURE_131)
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/* debug registers */
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A(0xFD00, DBGSR, TRICORE_FEATURE_13)
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A(0xFD08, EXEVT, TRICORE_FEATURE_13)
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A(0xFD0C, CREVT, TRICORE_FEATURE_13)
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A(0xFD10, SWEVT, TRICORE_FEATURE_13)
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A(0xFD20, TR0EVT, TRICORE_FEATURE_13)
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A(0xFD24, TR1EVT, TRICORE_FEATURE_13)
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A(0xFD40, DMS, TRICORE_FEATURE_13)
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A(0xFD44, DCX, TRICORE_FEATURE_13)
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A(0xFD48, DBGTCR, TRICORE_FEATURE_131)
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A(0xFC00, CCTRL, TRICORE_FEATURE_131)
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A(0xFC04, CCNT, TRICORE_FEATURE_131)
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A(0xFC08, ICNT, TRICORE_FEATURE_131)
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A(0xFC0C, M1CNT, TRICORE_FEATURE_131)
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A(0xFC10, M2CNT, TRICORE_FEATURE_131)
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A(0xFC14, M3CNT, TRICORE_FEATURE_131)
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@ -17,7 +17,21 @@
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/* Arithmetic */
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DEF_HELPER_3(add_ssov, i32, env, i32, i32)
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DEF_HELPER_3(add_suov, i32, env, i32, i32)
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DEF_HELPER_3(sub_ssov, i32, env, i32, i32)
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DEF_HELPER_3(sub_suov, i32, env, i32, i32)
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DEF_HELPER_3(mul_ssov, i32, env, i32, i32)
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DEF_HELPER_3(mul_suov, i32, env, i32, i32)
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DEF_HELPER_3(sha_ssov, i32, env, i32, i32)
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DEF_HELPER_3(absdif_ssov, i32, env, i32, i32)
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DEF_HELPER_4(madd32_ssov, i32, env, i32, i32, i32)
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DEF_HELPER_4(madd32_suov, i32, env, i32, i32, i32)
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DEF_HELPER_4(madd64_ssov, i64, env, i32, i64, i32)
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DEF_HELPER_4(madd64_suov, i64, env, i32, i64, i32)
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DEF_HELPER_4(msub32_ssov, i32, env, i32, i32, i32)
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DEF_HELPER_4(msub32_suov, i32, env, i32, i32, i32)
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DEF_HELPER_4(msub64_ssov, i64, env, i32, i64, i32)
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DEF_HELPER_4(msub64_suov, i64, env, i32, i64, i32)
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/* CSA */
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DEF_HELPER_2(call, void, env, i32)
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DEF_HELPER_1(ret, void, env)
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@ -30,3 +44,6 @@ DEF_HELPER_2(stucx, void, env, i32)
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/* Address mode helper */
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DEF_HELPER_1(br_update, i32, i32)
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DEF_HELPER_2(circ_update, i32, i32, i32)
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/* PSW cache helper */
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DEF_HELPER_2(psw_write, void, env, i32)
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DEF_HELPER_1(psw_read, i32, env)
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@ -77,6 +77,27 @@ uint32_t helper_circ_update(uint32_t reg, uint32_t off)
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env->PSW_USB_SAV |= env->PSW_USB_AV; \
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} while (0)
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#define SUOV(env, ret, arg, len) do { \
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int64_t max_pos = UINT##len ##_MAX; \
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if (arg > max_pos) { \
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env->PSW_USB_V = (1 << 31); \
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env->PSW_USB_SV = (1 << 31); \
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ret = (target_ulong)max_pos; \
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} else { \
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if (arg < 0) { \
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env->PSW_USB_V = (1 << 31); \
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env->PSW_USB_SV = (1 << 31); \
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ret = 0; \
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} else { \
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env->PSW_USB_V = 0; \
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ret = (target_ulong)arg; \
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} \
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} \
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env->PSW_USB_AV = arg ^ arg * 2u; \
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env->PSW_USB_SAV |= env->PSW_USB_AV; \
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} while (0)
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target_ulong helper_add_ssov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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@ -88,6 +109,17 @@ target_ulong helper_add_ssov(CPUTriCoreState *env, target_ulong r1,
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return ret;
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}
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target_ulong helper_add_suov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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target_ulong ret;
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int64_t t1 = extract64(r1, 0, 32);
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int64_t t2 = extract64(r2, 0, 32);
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int64_t result = t1 + t2;
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SUOV(env, ret, result, 32);
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return ret;
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}
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target_ulong helper_sub_ssov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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@ -99,6 +131,241 @@ target_ulong helper_sub_ssov(CPUTriCoreState *env, target_ulong r1,
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return ret;
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}
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target_ulong helper_sub_suov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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target_ulong ret;
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int64_t t1 = extract64(r1, 0, 32);
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int64_t t2 = extract64(r2, 0, 32);
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int64_t result = t1 - t2;
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SUOV(env, ret, result, 32);
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return ret;
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}
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target_ulong helper_mul_ssov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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target_ulong ret;
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int64_t t1 = sextract64(r1, 0, 32);
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int64_t t2 = sextract64(r2, 0, 32);
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int64_t result = t1 * t2;
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SSOV(env, ret, result, 32);
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return ret;
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}
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target_ulong helper_mul_suov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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target_ulong ret;
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int64_t t1 = extract64(r1, 0, 32);
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int64_t t2 = extract64(r2, 0, 32);
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int64_t result = t1 * t2;
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SUOV(env, ret, result, 32);
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return ret;
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}
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target_ulong helper_sha_ssov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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target_ulong ret;
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int64_t t1 = sextract64(r1, 0, 32);
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int32_t t2 = sextract64(r2, 0, 6);
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int64_t result;
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if (t2 == 0) {
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result = t1;
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} else if (t2 > 0) {
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result = t1 << t2;
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} else {
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result = t1 >> -t2;
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}
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SSOV(env, ret, result, 32);
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return ret;
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}
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target_ulong helper_absdif_ssov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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target_ulong ret;
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int64_t t1 = sextract64(r1, 0, 32);
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int64_t t2 = sextract64(r2, 0, 32);
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int64_t result;
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if (t1 > t2) {
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result = t1 - t2;
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} else {
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result = t2 - t1;
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}
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SSOV(env, ret, result, 32);
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return ret;
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}
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target_ulong helper_madd32_ssov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2, target_ulong r3)
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{
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target_ulong ret;
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int64_t t1 = sextract64(r1, 0, 32);
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int64_t t2 = sextract64(r2, 0, 32);
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int64_t t3 = sextract64(r3, 0, 32);
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int64_t result;
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result = t2 + (t1 * t3);
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SSOV(env, ret, result, 32);
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return ret;
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}
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target_ulong helper_madd32_suov(CPUTriCoreState *env, target_ulong r1,
|
||||
target_ulong r2, target_ulong r3)
|
||||
{
|
||||
target_ulong ret;
|
||||
uint64_t t1 = extract64(r1, 0, 32);
|
||||
uint64_t t2 = extract64(r2, 0, 32);
|
||||
uint64_t t3 = extract64(r3, 0, 32);
|
||||
int64_t result;
|
||||
|
||||
result = t2 + (t1 * t3);
|
||||
SUOV(env, ret, result, 32);
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint64_t helper_madd64_ssov(CPUTriCoreState *env, target_ulong r1,
|
||||
uint64_t r2, target_ulong r3)
|
||||
{
|
||||
uint64_t ret, ovf;
|
||||
int64_t t1 = sextract64(r1, 0, 32);
|
||||
int64_t t3 = sextract64(r3, 0, 32);
|
||||
int64_t mul;
|
||||
|
||||
mul = t1 * t3;
|
||||
ret = mul + r2;
|
||||
ovf = (ret ^ mul) & ~(mul ^ r2);
|
||||
|
||||
if ((int64_t)ovf < 0) {
|
||||
env->PSW_USB_V = (1 << 31);
|
||||
env->PSW_USB_SV = (1 << 31);
|
||||
/* ext_ret > MAX_INT */
|
||||
if (mul >= 0) {
|
||||
ret = INT64_MAX;
|
||||
/* ext_ret < MIN_INT */
|
||||
} else {
|
||||
ret = INT64_MIN;
|
||||
}
|
||||
} else {
|
||||
env->PSW_USB_V = 0;
|
||||
}
|
||||
t1 = ret >> 32;
|
||||
env->PSW_USB_AV = t1 ^ t1 * 2u;
|
||||
env->PSW_USB_SAV |= env->PSW_USB_AV;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint64_t helper_madd64_suov(CPUTriCoreState *env, target_ulong r1,
|
||||
uint64_t r2, target_ulong r3)
|
||||
{
|
||||
uint64_t ret, mul;
|
||||
uint64_t t1 = extract64(r1, 0, 32);
|
||||
uint64_t t3 = extract64(r3, 0, 32);
|
||||
|
||||
mul = t1 * t3;
|
||||
ret = mul + r2;
|
||||
|
||||
if (ret < r2) {
|
||||
env->PSW_USB_V = (1 << 31);
|
||||
env->PSW_USB_SV = (1 << 31);
|
||||
/* saturate */
|
||||
ret = UINT64_MAX;
|
||||
} else {
|
||||
env->PSW_USB_V = 0;
|
||||
}
|
||||
t1 = ret >> 32;
|
||||
env->PSW_USB_AV = t1 ^ t1 * 2u;
|
||||
env->PSW_USB_SAV |= env->PSW_USB_AV;
|
||||
return ret;
|
||||
}
|
||||
|
||||
target_ulong helper_msub32_ssov(CPUTriCoreState *env, target_ulong r1,
|
||||
target_ulong r2, target_ulong r3)
|
||||
{
|
||||
target_ulong ret;
|
||||
int64_t t1 = sextract64(r1, 0, 32);
|
||||
int64_t t2 = sextract64(r2, 0, 32);
|
||||
int64_t t3 = sextract64(r3, 0, 32);
|
||||
int64_t result;
|
||||
|
||||
result = t2 - (t1 * t3);
|
||||
SSOV(env, ret, result, 32);
|
||||
return ret;
|
||||
}
|
||||
|
||||
target_ulong helper_msub32_suov(CPUTriCoreState *env, target_ulong r1,
|
||||
target_ulong r2, target_ulong r3)
|
||||
{
|
||||
target_ulong ret;
|
||||
int64_t t1 = extract64(r1, 0, 32);
|
||||
int64_t t2 = extract64(r2, 0, 32);
|
||||
int64_t t3 = extract64(r3, 0, 32);
|
||||
int64_t result;
|
||||
|
||||
result = t2 - (t1 * t3);
|
||||
SUOV(env, ret, result, 32);
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint64_t helper_msub64_ssov(CPUTriCoreState *env, target_ulong r1,
|
||||
uint64_t r2, target_ulong r3)
|
||||
{
|
||||
uint64_t ret, ovf;
|
||||
int64_t t1 = sextract64(r1, 0, 32);
|
||||
int64_t t3 = sextract64(r3, 0, 32);
|
||||
int64_t mul;
|
||||
|
||||
mul = t1 * t3;
|
||||
ret = r2 - mul;
|
||||
ovf = (ret ^ r2) & (mul ^ r2);
|
||||
|
||||
if ((int64_t)ovf < 0) {
|
||||
env->PSW_USB_V = (1 << 31);
|
||||
env->PSW_USB_SV = (1 << 31);
|
||||
/* ext_ret > MAX_INT */
|
||||
if (mul < 0) {
|
||||
ret = INT64_MAX;
|
||||
/* ext_ret < MIN_INT */
|
||||
} else {
|
||||
ret = INT64_MIN;
|
||||
}
|
||||
} else {
|
||||
env->PSW_USB_V = 0;
|
||||
}
|
||||
t1 = ret >> 32;
|
||||
env->PSW_USB_AV = t1 ^ t1 * 2u;
|
||||
env->PSW_USB_SAV |= env->PSW_USB_AV;
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint64_t helper_msub64_suov(CPUTriCoreState *env, target_ulong r1,
|
||||
uint64_t r2, target_ulong r3)
|
||||
{
|
||||
uint64_t ret, mul;
|
||||
uint64_t t1 = extract64(r1, 0, 32);
|
||||
uint64_t t3 = extract64(r3, 0, 32);
|
||||
|
||||
mul = t1 * t3;
|
||||
ret = r2 - mul;
|
||||
|
||||
if (ret > r2) {
|
||||
env->PSW_USB_V = (1 << 31);
|
||||
env->PSW_USB_SV = (1 << 31);
|
||||
/* saturate */
|
||||
ret = 0;
|
||||
} else {
|
||||
env->PSW_USB_V = 0;
|
||||
}
|
||||
t1 = ret >> 32;
|
||||
env->PSW_USB_AV = t1 ^ t1 * 2u;
|
||||
env->PSW_USB_SAV |= env->PSW_USB_AV;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* context save area (CSA) related helpers */
|
||||
|
||||
static int cdc_increment(target_ulong *psw)
|
||||
@ -437,6 +704,17 @@ void helper_stucx(CPUTriCoreState *env, uint32_t ea)
|
||||
save_context_upper(env, ea);
|
||||
}
|
||||
|
||||
void helper_psw_write(CPUTriCoreState *env, uint32_t arg)
|
||||
{
|
||||
psw_write(env, arg);
|
||||
}
|
||||
|
||||
uint32_t helper_psw_read(CPUTriCoreState *env)
|
||||
{
|
||||
return psw_read(env);
|
||||
}
|
||||
|
||||
|
||||
static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *env,
|
||||
uint32_t exception,
|
||||
int error_code,
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -115,25 +115,31 @@
|
||||
#define MASK_OP_BOL_OFF16(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
|
||||
(MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
|
||||
(MASK_BITS_SHIFT(op, 22, 27) >> 10))
|
||||
|
||||
#define MASK_OP_BOL_OFF16_SEXT(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
|
||||
(MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
|
||||
(MASK_BITS_SHIFT_SEXT(op, 22, 27) << 10))
|
||||
#define MASK_OP_BOL_S2(op) MASK_BITS_SHIFT(op, 12, 15)
|
||||
#define MASK_OP_BOL_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
|
||||
|
||||
/* BRC Format */
|
||||
#define MASK_OP_BRC_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
|
||||
#define MASK_OP_BRC_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
|
||||
#define MASK_OP_BRC_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
|
||||
#define MASK_OP_BRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
|
||||
#define MASK_OP_BRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
|
||||
#define MASK_OP_BRC_S1(op) MASK_BITS_SHIFT(op, 8, 11)
|
||||
|
||||
/* BRN Format */
|
||||
#define MASK_OP_BRN_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
|
||||
#define MASK_OP_BRN_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
|
||||
#define MASK_OP_BRN_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
|
||||
#define MASK_OP_BRN_N(op) (MASK_BITS_SHIFT(op, 12, 15) + \
|
||||
(MASK_BITS_SHIFT(op, 7, 7) << 4))
|
||||
#define MASK_OP_BRN_S1(op) MASK_BITS_SHIFT(op, 8, 11)
|
||||
/* BRR Format */
|
||||
#define MASK_OP_BRR_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
|
||||
#define MASK_OP_BRR_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
|
||||
#define MASK_OP_BRR_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
|
||||
#define MASK_OP_BRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
|
||||
#define MASK_OP_BRR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
|
||||
|
||||
@ -145,6 +151,7 @@
|
||||
#define MASK_OP_RC_D(op) MASK_OP_META_D(op)
|
||||
#define MASK_OP_RC_OP2(op) MASK_BITS_SHIFT(op, 21, 27)
|
||||
#define MASK_OP_RC_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
|
||||
#define MASK_OP_RC_CONST9_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 20)
|
||||
#define MASK_OP_RC_S1(op) MASK_OP_META_S1(op)
|
||||
|
||||
/* RCPW Format */
|
||||
@ -162,6 +169,7 @@
|
||||
#define MASK_OP_RCR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
|
||||
#define MASK_OP_RCR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
|
||||
#define MASK_OP_RCR_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
|
||||
#define MASK_OP_RCR_CONST9_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 20)
|
||||
#define MASK_OP_RCR_S1(op) MASK_OP_META_S1(op)
|
||||
|
||||
/* RCRR Format */
|
||||
@ -185,6 +193,7 @@
|
||||
|
||||
#define MASK_OP_RLC_D(op) MASK_OP_META_D(op)
|
||||
#define MASK_OP_RLC_CONST16(op) MASK_BITS_SHIFT(op, 12, 27)
|
||||
#define MASK_OP_RLC_CONST16_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 27)
|
||||
#define MASK_OP_RLC_S1(op) MASK_OP_META_S1(op)
|
||||
|
||||
/* RR Format */
|
||||
@ -763,8 +772,8 @@ enum {
|
||||
};
|
||||
/* OPCM_32_BRC_GE */
|
||||
enum {
|
||||
OP2_BRC_JGE = 0x00,
|
||||
OPC_BRC_JGE_U = 0x01,
|
||||
OP2_32_BRC_JGE = 0x00,
|
||||
OPC_32_BRC_JGE_U = 0x01,
|
||||
};
|
||||
/* OPCM_32_BRC_JLT */
|
||||
enum {
|
||||
@ -937,7 +946,7 @@ enum {
|
||||
OPC2_32_RCR_MSUB_64 = 0x03,
|
||||
OPC2_32_RCR_MSUBS_32 = 0x05,
|
||||
OPC2_32_RCR_MSUBS_64 = 0x07,
|
||||
OPC2_32_RCR_MSUB_U_32 = 0x02,
|
||||
OPC2_32_RCR_MSUB_U_64 = 0x02,
|
||||
OPC2_32_RCR_MSUBS_U_32 = 0x04,
|
||||
OPC2_32_RCR_MSUBS_U_64 = 0x06,
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user