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target-mips: distinguish between data load and instruction fetch

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Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
This commit is contained in:
Leon Alrae 2014-07-07 11:23:57 +01:00
parent 55e9409366
commit 9f6bcedba6
1 changed files with 10 additions and 11 deletions
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21
target-mips/helper.c
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@ -87,7 +87,7 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
/* Check access rights */
if (!(n ? tlb->V1 : tlb->V0))
return TLBRET_INVALID;
if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
*physical = tlb->PFN[n] | (address & (mask >> 1));
*prot = PAGE_READ;
if (n ? tlb->D1 : tlb->D0)
@ -237,25 +237,28 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
case TLBRET_BADADDR:
/* Reference to kernel address from user mode or supervisor mode */
/* Reference to supervisor address from user mode */
if (rw)
if (rw == MMU_DATA_STORE) {
exception = EXCP_AdES;
else
} else {
exception = EXCP_AdEL;
}
break;
case TLBRET_NOMATCH:
/* No TLB match for a mapped address */
if (rw)
if (rw == MMU_DATA_STORE) {
exception = EXCP_TLBS;
else
} else {
exception = EXCP_TLBL;
}
error_code = 1;
break;
case TLBRET_INVALID:
/* TLB match with no valid bit */
if (rw)
if (rw == MMU_DATA_STORE) {
exception = EXCP_TLBS;
else
} else {
exception = EXCP_TLBL;
}
break;
case TLBRET_DIRTY:
/* TLB match but 'D' bit is cleared */
@ -312,8 +315,6 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, env->active_tc.PC, address, rw, mmu_idx);
rw &= 1;
/* data access */
#if !defined(CONFIG_USER_ONLY)
/* XXX: put correct access by using cpu_restore_state()
@ -347,8 +348,6 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int r
int access_type;
int ret = 0;
rw &= 1;
/* data access */
access_type = ACCESS_INT;
ret = get_physical_address(env, &physical, &prot,