hw/misc: versal: Add a model of the XRAM controller
Add a model of the Xilinx Versal Accelerator RAM (XRAM). This is mainly a stub to make firmware happy. The size of the RAMs can be probed. The interrupt mask logic is modelled but none of the interrups will ever be raised unless injected. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210308224637.2949533-2-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Edgar E. Iglesias
Peter Maydell
parent
6f34661b6c
commit
9f61763574
@ -85,6 +85,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
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))
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softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
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softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
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softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-xramc.c'))
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softmmu_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c'))
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softmmu_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c'))
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softmmu_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_exti.c'))
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253
hw/misc/xlnx-versal-xramc.c
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253
hw/misc/xlnx-versal-xramc.c
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@ -0,0 +1,253 @@
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/*
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* QEMU model of the Xilinx XRAM Controller.
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*
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* Copyright (c) 2021 Xilinx Inc.
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "migration/vmstate.h"
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#include "hw/qdev-properties.h"
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#include "hw/irq.h"
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#include "hw/misc/xlnx-versal-xramc.h"
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#ifndef XLNX_XRAM_CTRL_ERR_DEBUG
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#define XLNX_XRAM_CTRL_ERR_DEBUG 0
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#endif
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static void xram_update_irq(XlnxXramCtrl *s)
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{
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bool pending = s->regs[R_XRAM_ISR] & ~s->regs[R_XRAM_IMR];
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qemu_set_irq(s->irq, pending);
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}
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static void xram_isr_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxXramCtrl *s = XLNX_XRAM_CTRL(reg->opaque);
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xram_update_irq(s);
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}
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static uint64_t xram_ien_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxXramCtrl *s = XLNX_XRAM_CTRL(reg->opaque);
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uint32_t val = val64;
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s->regs[R_XRAM_IMR] &= ~val;
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xram_update_irq(s);
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return 0;
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}
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static uint64_t xram_ids_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxXramCtrl *s = XLNX_XRAM_CTRL(reg->opaque);
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uint32_t val = val64;
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s->regs[R_XRAM_IMR] |= val;
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xram_update_irq(s);
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return 0;
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}
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static const RegisterAccessInfo xram_ctrl_regs_info[] = {
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{ .name = "XRAM_ERR_CTRL", .addr = A_XRAM_ERR_CTRL,
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.reset = 0xf,
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.rsvd = 0xfffffff0,
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},{ .name = "XRAM_ISR", .addr = A_XRAM_ISR,
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.rsvd = 0xfffff800,
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.w1c = 0x7ff,
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.post_write = xram_isr_postw,
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},{ .name = "XRAM_IMR", .addr = A_XRAM_IMR,
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.reset = 0x7ff,
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.rsvd = 0xfffff800,
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.ro = 0x7ff,
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},{ .name = "XRAM_IEN", .addr = A_XRAM_IEN,
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.rsvd = 0xfffff800,
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.pre_write = xram_ien_prew,
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},{ .name = "XRAM_IDS", .addr = A_XRAM_IDS,
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.rsvd = 0xfffff800,
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.pre_write = xram_ids_prew,
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},{ .name = "XRAM_ECC_CNTL", .addr = A_XRAM_ECC_CNTL,
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.rsvd = 0xfffffff8,
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},{ .name = "XRAM_CLR_EXE", .addr = A_XRAM_CLR_EXE,
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.rsvd = 0xffffff00,
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},{ .name = "XRAM_CE_FFA", .addr = A_XRAM_CE_FFA,
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.rsvd = 0xfff00000,
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.ro = 0xfffff,
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},{ .name = "XRAM_CE_FFD0", .addr = A_XRAM_CE_FFD0,
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.ro = 0xffffffff,
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},{ .name = "XRAM_CE_FFD1", .addr = A_XRAM_CE_FFD1,
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.ro = 0xffffffff,
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},{ .name = "XRAM_CE_FFD2", .addr = A_XRAM_CE_FFD2,
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.ro = 0xffffffff,
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},{ .name = "XRAM_CE_FFD3", .addr = A_XRAM_CE_FFD3,
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.ro = 0xffffffff,
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},{ .name = "XRAM_CE_FFE", .addr = A_XRAM_CE_FFE,
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.rsvd = 0xffff0000,
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.ro = 0xffff,
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},{ .name = "XRAM_UE_FFA", .addr = A_XRAM_UE_FFA,
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.rsvd = 0xfff00000,
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.ro = 0xfffff,
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},{ .name = "XRAM_UE_FFD0", .addr = A_XRAM_UE_FFD0,
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.ro = 0xffffffff,
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},{ .name = "XRAM_UE_FFD1", .addr = A_XRAM_UE_FFD1,
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.ro = 0xffffffff,
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},{ .name = "XRAM_UE_FFD2", .addr = A_XRAM_UE_FFD2,
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.ro = 0xffffffff,
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},{ .name = "XRAM_UE_FFD3", .addr = A_XRAM_UE_FFD3,
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.ro = 0xffffffff,
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},{ .name = "XRAM_UE_FFE", .addr = A_XRAM_UE_FFE,
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.rsvd = 0xffff0000,
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.ro = 0xffff,
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},{ .name = "XRAM_FI_D0", .addr = A_XRAM_FI_D0,
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},{ .name = "XRAM_FI_D1", .addr = A_XRAM_FI_D1,
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},{ .name = "XRAM_FI_D2", .addr = A_XRAM_FI_D2,
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},{ .name = "XRAM_FI_D3", .addr = A_XRAM_FI_D3,
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},{ .name = "XRAM_FI_SY", .addr = A_XRAM_FI_SY,
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.rsvd = 0xffff0000,
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},{ .name = "XRAM_RMW_UE_FFA", .addr = A_XRAM_RMW_UE_FFA,
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.rsvd = 0xfff00000,
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.ro = 0xfffff,
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},{ .name = "XRAM_FI_CNTR", .addr = A_XRAM_FI_CNTR,
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.rsvd = 0xff000000,
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},{ .name = "XRAM_IMP", .addr = A_XRAM_IMP,
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.reset = 0x4,
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.rsvd = 0xfffffff0,
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.ro = 0xf,
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},{ .name = "XRAM_PRDY_DBG", .addr = A_XRAM_PRDY_DBG,
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.reset = 0xffff,
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.rsvd = 0xffff0000,
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.ro = 0xffff,
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},{ .name = "XRAM_SAFETY_CHK", .addr = A_XRAM_SAFETY_CHK,
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}
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};
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static void xram_ctrl_reset_enter(Object *obj, ResetType type)
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{
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XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj);
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
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register_reset(&s->regs_info[i]);
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}
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ARRAY_FIELD_DP32(s->regs, XRAM_IMP, SIZE, s->cfg.encoded_size);
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}
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static void xram_ctrl_reset_hold(Object *obj)
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{
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XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj);
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xram_update_irq(s);
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}
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static const MemoryRegionOps xram_ctrl_ops = {
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.read = register_read_memory,
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.write = register_write_memory,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void xram_ctrl_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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XlnxXramCtrl *s = XLNX_XRAM_CTRL(dev);
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switch (s->cfg.size) {
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case 64 * KiB:
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s->cfg.encoded_size = 0;
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break;
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case 128 * KiB:
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s->cfg.encoded_size = 1;
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break;
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case 256 * KiB:
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s->cfg.encoded_size = 2;
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break;
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case 512 * KiB:
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s->cfg.encoded_size = 3;
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break;
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case 1 * MiB:
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s->cfg.encoded_size = 4;
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break;
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default:
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error_setg(errp, "Unsupported XRAM size %" PRId64, s->cfg.size);
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return;
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}
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memory_region_init_ram(&s->ram, OBJECT(s),
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object_get_canonical_path_component(OBJECT(s)),
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s->cfg.size, &error_fatal);
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sysbus_init_mmio(sbd, &s->ram);
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}
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static void xram_ctrl_init(Object *obj)
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{
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XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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s->reg_array =
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register_init_block32(DEVICE(obj), xram_ctrl_regs_info,
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ARRAY_SIZE(xram_ctrl_regs_info),
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s->regs_info, s->regs,
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&xram_ctrl_ops,
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XLNX_XRAM_CTRL_ERR_DEBUG,
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XRAM_CTRL_R_MAX * 4);
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sysbus_init_mmio(sbd, &s->reg_array->mem);
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sysbus_init_irq(sbd, &s->irq);
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}
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static void xram_ctrl_finalize(Object *obj)
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{
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XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj);
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register_finalize_block(s->reg_array);
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}
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static const VMStateDescription vmstate_xram_ctrl = {
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.name = TYPE_XLNX_XRAM_CTRL,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, XlnxXramCtrl, XRAM_CTRL_R_MAX),
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VMSTATE_END_OF_LIST(),
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}
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};
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static Property xram_ctrl_properties[] = {
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DEFINE_PROP_UINT64("size", XlnxXramCtrl, cfg.size, 1 * MiB),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void xram_ctrl_class_init(ObjectClass *klass, void *data)
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{
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = xram_ctrl_realize;
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dc->vmsd = &vmstate_xram_ctrl;
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device_class_set_props(dc, xram_ctrl_properties);
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rc->phases.enter = xram_ctrl_reset_enter;
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rc->phases.hold = xram_ctrl_reset_hold;
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}
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static const TypeInfo xram_ctrl_info = {
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.name = TYPE_XLNX_XRAM_CTRL,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(XlnxXramCtrl),
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.class_init = xram_ctrl_class_init,
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.instance_init = xram_ctrl_init,
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.instance_finalize = xram_ctrl_finalize,
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};
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static void xram_ctrl_register_types(void)
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{
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type_register_static(&xram_ctrl_info);
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}
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type_init(xram_ctrl_register_types)
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97
include/hw/misc/xlnx-versal-xramc.h
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97
include/hw/misc/xlnx-versal-xramc.h
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@ -0,0 +1,97 @@
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/*
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* QEMU model of the Xilinx XRAM Controller.
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*
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* Copyright (c) 2021 Xilinx Inc.
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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*/
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#ifndef XLNX_VERSAL_XRAMC_H
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#define XLNX_VERSAL_XRAMC_H
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#define TYPE_XLNX_XRAM_CTRL "xlnx.versal-xramc"
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#define XLNX_XRAM_CTRL(obj) \
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OBJECT_CHECK(XlnxXramCtrl, (obj), TYPE_XLNX_XRAM_CTRL)
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REG32(XRAM_ERR_CTRL, 0x0)
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FIELD(XRAM_ERR_CTRL, UE_RES, 3, 1)
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FIELD(XRAM_ERR_CTRL, PWR_ERR_RES, 2, 1)
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FIELD(XRAM_ERR_CTRL, PZ_ERR_RES, 1, 1)
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FIELD(XRAM_ERR_CTRL, APB_ERR_RES, 0, 1)
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REG32(XRAM_ISR, 0x4)
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FIELD(XRAM_ISR, INV_APB, 0, 1)
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REG32(XRAM_IMR, 0x8)
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FIELD(XRAM_IMR, INV_APB, 0, 1)
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REG32(XRAM_IEN, 0xc)
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FIELD(XRAM_IEN, INV_APB, 0, 1)
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REG32(XRAM_IDS, 0x10)
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FIELD(XRAM_IDS, INV_APB, 0, 1)
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REG32(XRAM_ECC_CNTL, 0x14)
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FIELD(XRAM_ECC_CNTL, FI_MODE, 2, 1)
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FIELD(XRAM_ECC_CNTL, DET_ONLY, 1, 1)
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FIELD(XRAM_ECC_CNTL, ECC_ON_OFF, 0, 1)
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REG32(XRAM_CLR_EXE, 0x18)
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FIELD(XRAM_CLR_EXE, MON_7, 7, 1)
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FIELD(XRAM_CLR_EXE, MON_6, 6, 1)
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FIELD(XRAM_CLR_EXE, MON_5, 5, 1)
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FIELD(XRAM_CLR_EXE, MON_4, 4, 1)
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FIELD(XRAM_CLR_EXE, MON_3, 3, 1)
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FIELD(XRAM_CLR_EXE, MON_2, 2, 1)
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FIELD(XRAM_CLR_EXE, MON_1, 1, 1)
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FIELD(XRAM_CLR_EXE, MON_0, 0, 1)
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REG32(XRAM_CE_FFA, 0x1c)
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FIELD(XRAM_CE_FFA, ADDR, 0, 20)
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REG32(XRAM_CE_FFD0, 0x20)
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REG32(XRAM_CE_FFD1, 0x24)
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REG32(XRAM_CE_FFD2, 0x28)
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REG32(XRAM_CE_FFD3, 0x2c)
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REG32(XRAM_CE_FFE, 0x30)
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FIELD(XRAM_CE_FFE, SYNDROME, 0, 16)
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REG32(XRAM_UE_FFA, 0x34)
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FIELD(XRAM_UE_FFA, ADDR, 0, 20)
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REG32(XRAM_UE_FFD0, 0x38)
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REG32(XRAM_UE_FFD1, 0x3c)
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REG32(XRAM_UE_FFD2, 0x40)
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REG32(XRAM_UE_FFD3, 0x44)
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REG32(XRAM_UE_FFE, 0x48)
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FIELD(XRAM_UE_FFE, SYNDROME, 0, 16)
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REG32(XRAM_FI_D0, 0x4c)
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REG32(XRAM_FI_D1, 0x50)
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REG32(XRAM_FI_D2, 0x54)
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REG32(XRAM_FI_D3, 0x58)
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REG32(XRAM_FI_SY, 0x5c)
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FIELD(XRAM_FI_SY, DATA, 0, 16)
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REG32(XRAM_RMW_UE_FFA, 0x70)
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FIELD(XRAM_RMW_UE_FFA, ADDR, 0, 20)
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REG32(XRAM_FI_CNTR, 0x74)
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FIELD(XRAM_FI_CNTR, COUNT, 0, 24)
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REG32(XRAM_IMP, 0x80)
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FIELD(XRAM_IMP, SIZE, 0, 4)
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REG32(XRAM_PRDY_DBG, 0x84)
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FIELD(XRAM_PRDY_DBG, ISLAND3, 12, 4)
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FIELD(XRAM_PRDY_DBG, ISLAND2, 8, 4)
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FIELD(XRAM_PRDY_DBG, ISLAND1, 4, 4)
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FIELD(XRAM_PRDY_DBG, ISLAND0, 0, 4)
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REG32(XRAM_SAFETY_CHK, 0xff8)
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#define XRAM_CTRL_R_MAX (R_XRAM_SAFETY_CHK + 1)
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typedef struct XlnxXramCtrl {
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SysBusDevice parent_obj;
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MemoryRegion ram;
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qemu_irq irq;
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struct {
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uint64_t size;
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unsigned int encoded_size;
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} cfg;
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RegisterInfoArray *reg_array;
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uint32_t regs[XRAM_CTRL_R_MAX];
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RegisterInfo regs_info[XRAM_CTRL_R_MAX];
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} XlnxXramCtrl;
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#endif
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