tcg/arm: Support TCG_COND_TST{EQ,NE}
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231028194522.245170-12-richard.henderson@linaro.org> [PMD: Split from bigger patch, part 2/2] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231108145244.72421-2-philmd@linaro.org>
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@ -1194,7 +1194,27 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
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static TCGCond tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg a,
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TCGArg b, int b_const)
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{
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tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b, b_const);
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if (!is_tst_cond(cond)) {
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tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b, b_const);
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return cond;
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}
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cond = tcg_tst_eqne_cond(cond);
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if (b_const) {
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int imm12 = encode_imm(b);
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/*
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* The compare constraints allow rIN, but TST does not support N.
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* Be prepared to load the constant into a scratch register.
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*/
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if (imm12 >= 0) {
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tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, a, imm12);
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return cond;
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}
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tcg_out_movi32(s, COND_AL, TCG_REG_TMP, b);
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b = TCG_REG_TMP;
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}
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tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, a, b, SHIFT_IMM_LSL(0));
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return cond;
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}
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@ -1225,6 +1245,13 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
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tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl);
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return cond;
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case TCG_COND_TSTEQ:
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case TCG_COND_TSTNE:
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/* Similar, but with TST instead of CMP. */
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tcg_out_dat_rI(s, COND_AL, ARITH_TST, 0, ah, bh, const_bh);
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tcg_out_dat_rI(s, COND_EQ, ARITH_TST, 0, al, bl, const_bl);
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return tcg_tst_eqne_cond(cond);
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case TCG_COND_LT:
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case TCG_COND_GE:
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/* We perform a double-word subtraction and examine the result.
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@ -125,7 +125,7 @@ extern bool use_neon_instructions;
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#define TCG_TARGET_HAS_qemu_ldst_i128 0
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#define TCG_TARGET_HAS_tst 0
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#define TCG_TARGET_HAS_tst 1
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#define TCG_TARGET_HAS_v64 use_neon_instructions
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#define TCG_TARGET_HAS_v128 use_neon_instructions
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