tcg-sparc: Remove most uses of TCG_TARGET_REG_BITS
Replace with SPARC64 define. Soon even sparcv8plus will use 64-bit register as far as TCG is concerned. Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
4bb7a41ed6
commit
9f44adc573
@ -61,6 +61,12 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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};
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#endif
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#ifdef __arch64__
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# define SPARC64 1
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#else
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# define SPARC64 0
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#endif
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/* Define some temporary registers. T2 is used for constant generation. */
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#define TCG_REG_T1 TCG_REG_G1
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#define TCG_REG_T2 TCG_REG_O7
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@ -402,9 +408,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
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}
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/* A 32-bit constant, or 32-bit zero-extended to 64-bits. */
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if (TCG_TARGET_REG_BITS == 32
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|| type == TCG_TYPE_I32
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|| (arg & ~0xffffffffu) == 0) {
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if (type == TCG_TYPE_I32 || (arg & ~0xffffffffu) == 0) {
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tcg_out_sethi(s, ret, arg);
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if (arg & 0x3ff) {
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tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
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@ -588,7 +592,7 @@ static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
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tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const);
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}
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#if TCG_TARGET_REG_BITS == 64
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#if SPARC64
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static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGArg arg1,
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TCGArg arg2, int const_arg2, int label)
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{
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@ -726,7 +730,7 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
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}
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}
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#if TCG_TARGET_REG_BITS == 64
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#if SPARC64
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static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGArg ret,
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TCGArg c1, TCGArg c2, int c2const)
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{
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@ -858,7 +862,7 @@ static void build_trampolines(TCGContext *s)
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qemu_ld_trampoline[i] = tramp;
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/* Find the retaddr argument register. */
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ra = TCG_REG_O3 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS);
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ra = TCG_REG_O3 + (!SPARC64 && TARGET_LONG_BITS == 64);
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/* Set the retaddr operand. */
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tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7);
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@ -885,8 +889,8 @@ static void build_trampolines(TCGContext *s)
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/* Find the retaddr argument. For 32-bit, this may be past the
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last argument register, and need passing on the stack. */
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ra = (TCG_REG_O4
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+ (TARGET_LONG_BITS > TCG_TARGET_REG_BITS)
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+ (TCG_TARGET_REG_BITS == 32 && (i & MO_SIZE) == MO_64));
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+ (!SPARC64 && TARGET_LONG_BITS == 64)
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+ (!SPARC64 && (i & MO_SIZE) == MO_64));
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/* Set the retaddr operand. */
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if (ra >= TCG_REG_O6) {
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@ -965,7 +969,7 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
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TCGReg addr = addrlo;
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int tlb_ofs;
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if (TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 64) {
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if (!SPARC64 && TARGET_LONG_BITS == 64) {
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/* Assemble the 64-bit address in R0. */
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tcg_out_arithi(s, r0, addrlo, 0, SHIFT_SRL);
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tcg_out_arithi(s, r1, addrhi, 32, SHIFT_SLLX);
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@ -1007,7 +1011,7 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
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tcg_out_cmp(s, r0, r2, 0);
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/* If the guest address must be zero-extended, do so now. */
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if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) {
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if (SPARC64 && TARGET_LONG_BITS == 32) {
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tcg_out_arithi(s, r0, addrlo, 0, SHIFT_SRL);
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return r0;
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}
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@ -1056,9 +1060,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
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#endif
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datalo = *args++;
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datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0);
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datahi = (!SPARC64 && is64 ? *args++ : 0);
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addrlo = *args++;
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addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
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addrhi = (!SPARC64 && TARGET_LONG_BITS == 64 ? *args++ : 0);
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memop = *args++;
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s_bits = memop & MO_SIZE;
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@ -1067,7 +1071,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
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addrz = tcg_out_tlb_load(s, addrlo, addrhi, memi, s_bits,
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offsetof(CPUTLBEntry, addr_read));
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if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
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if (!SPARC64 && s_bits == MO_64) {
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int reg64;
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/* bne,pn %[xi]cc, label0 */
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@ -1149,11 +1153,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
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*label_ptr[1] |= INSN_OFF19((unsigned long)s->code_ptr -
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(unsigned long)label_ptr[1]);
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#else
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if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) {
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if (SPARC64 && TARGET_LONG_BITS == 32) {
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tcg_out_arithi(s, TCG_REG_T1, addrlo, 0, SHIFT_SRL);
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addrlo = TCG_REG_T1;
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}
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if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
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if (!SPARC64 && s_bits == MO_64) {
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int reg64 = (datalo < 16 ? datalo : TCG_REG_O0);
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tcg_out_ldst_rr(s, reg64, addrlo,
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@ -1184,9 +1188,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
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#endif
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datalo = *args++;
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datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0);
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datahi = (!SPARC64 && is64 ? *args++ : 0);
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addrlo = *args++;
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addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
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addrhi = (!SPARC64 && TARGET_LONG_BITS == 64 ? *args++ : 0);
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memop = *args++;
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s_bits = memop & MO_SIZE;
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@ -1196,7 +1200,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
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offsetof(CPUTLBEntry, addr_write));
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datafull = datalo;
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if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
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if (!SPARC64 && s_bits == MO_64) {
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/* Reconstruct the full 64-bit value. */
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tcg_out_arithi(s, TCG_REG_T1, datalo, 0, SHIFT_SRL);
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tcg_out_arithi(s, TCG_REG_O2, datahi, 32, SHIFT_SLLX);
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@ -1234,11 +1238,11 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
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*label_ptr |= INSN_OFF19((unsigned long)s->code_ptr -
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(unsigned long)label_ptr);
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#else
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if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) {
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if (SPARC64 && TARGET_LONG_BITS == 32) {
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tcg_out_arithi(s, TCG_REG_T1, addrlo, 0, SHIFT_SRL);
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addrlo = TCG_REG_T1;
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}
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if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
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if (!SPARC64 && s_bits == MO_64) {
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tcg_out_arithi(s, TCG_REG_T1, datalo, 0, SHIFT_SRL);
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tcg_out_arithi(s, TCG_REG_O2, datahi, 32, SHIFT_SLLX);
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tcg_out_arith(s, TCG_REG_O2, TCG_REG_T1, TCG_REG_O2, ARITH_OR);
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@ -1294,7 +1298,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
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break;
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#if TCG_TARGET_REG_BITS == 64
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#if SPARC64
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#define OP_32_64(x) \
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glue(glue(case INDEX_op_, x), _i32): \
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glue(glue(case INDEX_op_, x), _i64)
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@ -1315,7 +1319,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
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break;
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case INDEX_op_ld_i32:
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#if TCG_TARGET_REG_BITS == 64
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#if SPARC64
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case INDEX_op_ld32u_i64:
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#endif
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tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
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@ -1327,7 +1331,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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tcg_out_ldst(s, args[0], args[1], args[2], STH);
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break;
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case INDEX_op_st_i32:
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#if TCG_TARGET_REG_BITS == 64
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#if SPARC64
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case INDEX_op_st32_i64:
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#endif
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tcg_out_ldst(s, args[0], args[1], args[2], STW);
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@ -1396,7 +1400,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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args[2], const_args[2], args[3], const_args[3]);
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break;
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#if TCG_TARGET_REG_BITS == 32
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#if !SPARC64
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case INDEX_op_brcond2_i32:
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tcg_out_brcond2_i32(s, args[4], args[0], args[1],
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args[2], const_args[2],
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@ -1438,7 +1442,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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tcg_out_qemu_st(s, args, 1);
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break;
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#if TCG_TARGET_REG_BITS == 64
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#if SPARC64
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case INDEX_op_movi_i64:
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tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
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break;
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@ -1545,7 +1549,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
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{ INDEX_op_setcond_i32, { "r", "rZ", "rJ" } },
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{ INDEX_op_movcond_i32, { "r", "rZ", "rJ", "rI", "0" } },
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#if TCG_TARGET_REG_BITS == 32
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#if !SPARC64
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{ INDEX_op_brcond2_i32, { "rZ", "rZ", "rJ", "rJ" } },
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{ INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rJ", "rJ" } },
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#endif
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@ -1554,7 +1558,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
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{ INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
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{ INDEX_op_mulu2_i32, { "r", "r", "rZ", "rJ" } },
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#if TCG_TARGET_REG_BITS == 64
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#if SPARC64
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{ INDEX_op_mov_i64, { "r", "r" } },
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{ INDEX_op_movi_i64, { "r" } },
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{ INDEX_op_ld8u_i64, { "r", "r" } },
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@ -1595,12 +1599,12 @@ static const TCGTargetOpDef sparc_op_defs[] = {
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{ INDEX_op_movcond_i64, { "r", "rZ", "rJ", "rI", "0" } },
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#endif
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#if TCG_TARGET_REG_BITS == 64
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#if SPARC64
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{ INDEX_op_qemu_ld_i32, { "r", "L" } },
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{ INDEX_op_qemu_ld_i64, { "r", "L" } },
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{ INDEX_op_qemu_st_i32, { "L", "L" } },
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{ INDEX_op_qemu_st_i64, { "L", "L" } },
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#elif TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
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#elif TARGET_LONG_BITS == 32
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{ INDEX_op_qemu_ld_i32, { "r", "L" } },
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{ INDEX_op_qemu_ld_i64, { "r", "r", "L" } },
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{ INDEX_op_qemu_st_i32, { "L", "L" } },
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@ -1618,7 +1622,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
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static void tcg_target_init(TCGContext *s)
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{
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tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
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#if TCG_TARGET_REG_BITS == 64
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#if SPARC64
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tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
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#endif
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tcg_regset_set32(tcg_target_call_clobber_regs, 0,
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@ -1650,7 +1654,7 @@ static void tcg_target_init(TCGContext *s)
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tcg_add_target_add_op_defs(sparc_op_defs);
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}
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#if TCG_TARGET_REG_BITS == 64
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#if SPARC64
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# define ELF_HOST_MACHINE EM_SPARCV9
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#else
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# define ELF_HOST_MACHINE EM_SPARC32PLUS
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@ -1660,7 +1664,7 @@ static void tcg_target_init(TCGContext *s)
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typedef struct {
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DebugFrameCIE cie;
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DebugFrameFDEHeader fde;
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uint8_t fde_def_cfa[TCG_TARGET_REG_BITS == 64 ? 4 : 2];
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uint8_t fde_def_cfa[SPARC64 ? 4 : 2];
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uint8_t fde_win_save;
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uint8_t fde_ret_save[3];
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} DebugFrame;
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@ -1677,7 +1681,7 @@ static DebugFrame debug_frame = {
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.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
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.fde_def_cfa = {
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#if TCG_TARGET_REG_BITS == 64
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#if SPARC64
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12, 30, /* DW_CFA_def_cfa i6, 2047 */
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(2047 & 0x7f) | 0x80, (2047 >> 7)
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#else
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