rc4030 registers improvements
Attached patch documents some registers and simplifies one hack. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7030 c046a42c-6fe2-441c-8c8c-71466251a162
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aurel32
parent
b09d9d4618
commit
9ea0b7a139
119
hw/rc4030.c
119
hw/rc4030.c
@ -1,7 +1,7 @@
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/*
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* QEMU JAZZ RC4030 chipset
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*
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* Copyright (c) 2007-2008 Hervé Poussineau
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* Copyright (c) 2007-2009 Herve Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -66,6 +66,7 @@ typedef struct dma_pagetable_entry {
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typedef struct rc4030State
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{
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uint32_t config; /* 0x0000: RC4030 config register */
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uint32_t revision; /* 0x0008: RC4030 Revision register */
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uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
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/* DMA */
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@ -74,17 +75,17 @@ typedef struct rc4030State
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uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
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/* cache */
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uint32_t cache_maint; /* 0x0030: Cache Maintenance */
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uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
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uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
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uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
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uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
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uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
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uint32_t cache_bwin; /* 0x0060: I/O Cache Buffer Window */
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uint32_t nmi_interrupt; /* 0x0200: interrupt source */
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uint32_t offset210;
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uint32_t nvram_protect; /* 0x0220: NV ram protect register */
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uint32_t offset238;
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uint32_t rem_speed[15];
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uint32_t rem_speed[16];
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uint32_t imr_jazz; /* Local bus int enable mask */
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uint32_t isr_jazz; /* Local bus int source */
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@ -118,6 +119,10 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
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case 0x0000:
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val = s->config;
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break;
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/* Revision register */
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case 0x0008:
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val = s->revision;
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break;
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/* Invalid Address register */
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case 0x0010:
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val = s->invalid_address_register;
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@ -161,6 +166,7 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
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case 0x00d0:
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case 0x00d8:
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case 0x00e0:
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case 0x00e8:
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val = s->rem_speed[(addr - 0x0070) >> 3];
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break;
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/* DMA channel base address */
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@ -202,7 +208,11 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
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val = s->dma_regs[entry][idx];
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}
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break;
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/* Offset 0x0208 */
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/* Interrupt source */
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case 0x0200:
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val = s->nmi_interrupt;
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break;
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/* Error type */
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case 0x0208:
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val = 0;
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break;
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@ -219,9 +229,9 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
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val = 0;
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qemu_irq_lower(s->timer_irq);
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break;
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/* Offset 0x0238 */
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/* EISA interrupt */
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case 0x0238:
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val = s->offset238;
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val = 7; /* FIXME: should be read from EISA controller */
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break;
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default:
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RC4030_ERROR("invalid read [" TARGET_FMT_plx "]\n", addr);
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@ -275,7 +285,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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break;
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/* Cache Maintenance */
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case 0x0030:
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RC4030_ERROR("Cache maintenance not handled yet (val 0x%02x)\n", val);
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s->cache_maint = val;
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break;
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/* I/O Cache Physical Tag */
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case 0x0048:
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@ -291,16 +301,11 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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break;
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/* I/O Cache Buffer Window */
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case 0x0060:
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s->cache_bwin = val;
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/* HACK */
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if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
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target_phys_addr_t dests[] = { 4, 0, 8, 0x10 };
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static int current = 0;
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target_phys_addr_t dest = 0 + dests[current];
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uint8_t buf;
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current = (current + 1) % (ARRAY_SIZE(dests));
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buf = s->cache_bwin - 1;
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cpu_physical_memory_rw(dest, &buf, 1, 1);
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target_phys_addr_t dest = s->cache_ptag & ~0x1;
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dest += (s->cache_maint & 0x3) << 3;
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cpu_physical_memory_rw(dest, (uint8_t*)&val, 4, 1);
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}
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break;
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/* Remote Speed Registers */
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@ -319,6 +324,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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case 0x00d0:
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case 0x00d8:
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case 0x00e0:
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case 0x00e8:
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s->rem_speed[(addr - 0x0070) >> 3] = val;
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break;
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/* DMA channel base address */
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@ -370,6 +376,9 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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qemu_irq_lower(s->timer_irq);
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set_next_tick(s);
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break;
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/* EISA interrupt */
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case 0x0238:
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break;
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default:
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RC4030_ERROR("invalid write of 0x%02x at [" TARGET_FMT_plx "]\n", val, addr);
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break;
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@ -580,21 +589,23 @@ static void rc4030_reset(void *opaque)
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int i;
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s->config = 0x410; /* some boards seem to accept 0x104 too */
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s->revision = 1;
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s->invalid_address_register = 0;
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memset(s->dma_regs, 0, sizeof(s->dma_regs));
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s->dma_tl_base = s->dma_tl_limit = 0;
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s->remote_failed_address = s->memory_failed_address = 0;
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s->cache_maint = 0;
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s->cache_ptag = s->cache_ltag = 0;
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s->cache_bmask = s->cache_bwin = 0;
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s->cache_bmask = 0;
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s->offset210 = 0x18186;
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s->nvram_protect = 7;
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s->offset238 = 7;
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for (i = 0; i < 15; i++)
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s->rem_speed[i] = 7;
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s->imr_jazz = s->isr_jazz = 0;
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s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */
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s->isr_jazz = 0;
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s->itr = 0;
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@ -607,7 +618,7 @@ static int rc4030_load(QEMUFile *f, void *opaque, int version_id)
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rc4030State* s = opaque;
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int i, j;
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if (version_id != 1)
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if (version_id != 2)
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return -EINVAL;
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s->config = qemu_get_be32(f);
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@ -617,15 +628,14 @@ static int rc4030_load(QEMUFile *f, void *opaque, int version_id)
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s->dma_regs[i][j] = qemu_get_be32(f);
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s->dma_tl_base = qemu_get_be32(f);
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s->dma_tl_limit = qemu_get_be32(f);
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s->cache_maint = qemu_get_be32(f);
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s->remote_failed_address = qemu_get_be32(f);
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s->memory_failed_address = qemu_get_be32(f);
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s->cache_ptag = qemu_get_be32(f);
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s->cache_ltag = qemu_get_be32(f);
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s->cache_bmask = qemu_get_be32(f);
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s->cache_bwin = qemu_get_be32(f);
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s->offset210 = qemu_get_be32(f);
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s->nvram_protect = qemu_get_be32(f);
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s->offset238 = qemu_get_be32(f);
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for (i = 0; i < 15; i++)
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s->rem_speed[i] = qemu_get_be32(f);
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s->imr_jazz = qemu_get_be32(f);
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@ -650,15 +660,14 @@ static void rc4030_save(QEMUFile *f, void *opaque)
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qemu_put_be32(f, s->dma_regs[i][j]);
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qemu_put_be32(f, s->dma_tl_base);
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qemu_put_be32(f, s->dma_tl_limit);
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qemu_put_be32(f, s->cache_maint);
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qemu_put_be32(f, s->remote_failed_address);
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qemu_put_be32(f, s->memory_failed_address);
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qemu_put_be32(f, s->cache_ptag);
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qemu_put_be32(f, s->cache_ltag);
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qemu_put_be32(f, s->cache_bmask);
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qemu_put_be32(f, s->cache_bwin);
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qemu_put_be32(f, s->offset210);
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qemu_put_be32(f, s->nvram_protect);
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qemu_put_be32(f, s->offset238);
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for (i = 0; i < 15; i++)
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qemu_put_be32(f, s->rem_speed[i]);
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qemu_put_be32(f, s->imr_jazz);
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@ -666,44 +675,28 @@ static void rc4030_save(QEMUFile *f, void *opaque)
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qemu_put_be32(f, s->itr);
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}
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static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
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static void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)
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{
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rc4030State *s = opaque;
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target_phys_addr_t entry_addr;
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target_phys_addr_t dma_addr, phys_addr;
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target_phys_addr_t phys_addr;
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dma_pagetable_entry entry;
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int index, dev_to_mem;
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int index;
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int ncpy, i;
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s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
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/* Check DMA channel consistency */
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dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1;
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if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
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(is_write != dev_to_mem)) {
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s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
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return;
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}
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if (len > s->dma_regs[n][DMA_REG_COUNT])
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len = s->dma_regs[n][DMA_REG_COUNT];
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dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];
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i = 0;
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for (;;) {
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if (i == len) {
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s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR;
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break;
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}
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ncpy = DMA_PAGESIZE - (dma_addr & (DMA_PAGESIZE - 1));
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ncpy = DMA_PAGESIZE - (addr & (DMA_PAGESIZE - 1));
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if (ncpy > len - i)
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ncpy = len - i;
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/* Get DMA translation table entry */
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index = dma_addr / DMA_PAGESIZE;
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index = addr / DMA_PAGESIZE;
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if (index >= s->dma_tl_limit / sizeof(dma_pagetable_entry)) {
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s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
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break;
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}
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entry_addr = s->dma_tl_base + index * sizeof(dma_pagetable_entry);
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@ -712,13 +705,41 @@ static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_wri
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cpu_physical_memory_rw(entry_addr, (uint8_t *)&entry, sizeof(entry), 0);
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/* Read/write data at right place */
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phys_addr = entry.frame + (dma_addr & (DMA_PAGESIZE - 1));
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phys_addr = entry.frame + (addr & (DMA_PAGESIZE - 1));
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cpu_physical_memory_rw(phys_addr, &buf[i], ncpy, is_write);
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i += ncpy;
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dma_addr += ncpy;
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s->dma_regs[n][DMA_REG_COUNT] -= ncpy;
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addr += ncpy;
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}
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}
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static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
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{
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rc4030State *s = opaque;
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target_phys_addr_t dma_addr;
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int dev_to_mem;
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s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
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/* Check DMA channel consistency */
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dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1;
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if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
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(is_write != dev_to_mem)) {
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s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
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s->nmi_interrupt |= 1 << n;
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return;
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}
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/* Get start address and len */
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if (len > s->dma_regs[n][DMA_REG_COUNT])
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len = s->dma_regs[n][DMA_REG_COUNT];
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dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];
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/* Read/write data at right place */
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rc4030_dma_memory_rw(opaque, dma_addr, buf, len, is_write);
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s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR;
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s->dma_regs[n][DMA_REG_COUNT] -= len;
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#ifdef DEBUG_RC4030_DMA
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{
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@ -792,7 +813,7 @@ qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
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s->jazz_bus_irq = jazz_bus;
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qemu_register_reset(rc4030_reset, s);
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register_savevm("rc4030", 0, 1, rc4030_save, rc4030_load, s);
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register_savevm("rc4030", 0, 2, rc4030_save, rc4030_load, s);
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rc4030_reset(s);
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s_chipset = cpu_register_io_memory(0, rc4030_read, rc4030_write, s);
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