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accel-cpu: make cpu_realizefn return a bool

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overall, all devices' realize functions take an Error **errp, but return void.

hw/core/qdev.c code, which realizes devices, therefore does:

local_err = NULL;
dc->realize(dev, &local_err);
if (local_err != NULL) {
    goto fail;
}

However, we can improve at least accel_cpu to return a meaningful bool value.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210322132800.7470-9-cfontana@suse.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Claudio Fontana 2021-03-22 14:27:44 +01:00 committed by Paolo Bonzini
parent ce21726525
commit 9ea057dc64
8 changed files with 18 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
accel/accel-common.c
View File

@ -98,14 +98,14 @@ void accel_cpu_instance_init(CPUState *cpu)
} }
} }
void accel_cpu_realizefn(CPUState *cpu, Error **errp) bool accel_cpu_realizefn(CPUState *cpu, Error **errp)
{ {
CPUClass *cc = CPU_GET_CLASS(cpu); CPUClass *cc = CPU_GET_CLASS(cpu);
if (cc->accel_cpu && cc->accel_cpu->cpu_realizefn) { if (cc->accel_cpu && cc->accel_cpu->cpu_realizefn) {
/* NB: errp parameter is unused currently */ return cc->accel_cpu->cpu_realizefn(cpu, errp);
cc->accel_cpu->cpu_realizefn(cpu, errp);
} }
return true;
} }
static const TypeInfo accel_cpu_type = { static const TypeInfo accel_cpu_type = {

5
cpu.c
View File

@ -130,8 +130,9 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
CPUClass *cc = CPU_GET_CLASS(cpu); CPUClass *cc = CPU_GET_CLASS(cpu);
cpu_list_add(cpu); cpu_list_add(cpu);
accel_cpu_realizefn(cpu, errp); if (!accel_cpu_realizefn(cpu, errp)) {
return;
}
#ifdef CONFIG_TCG #ifdef CONFIG_TCG
/* NB: errp parameter is unused currently */ /* NB: errp parameter is unused currently */
if (tcg_enabled()) { if (tcg_enabled()) {

2
include/hw/core/accel-cpu.h
View File

@ -32,7 +32,7 @@ typedef struct AccelCPUClass {
void (*cpu_class_init)(CPUClass *cc); void (*cpu_class_init)(CPUClass *cc);
void (*cpu_instance_init)(CPUState *cpu); void (*cpu_instance_init)(CPUState *cpu);
void (*cpu_realizefn)(CPUState *cpu, Error **errp); bool (*cpu_realizefn)(CPUState *cpu, Error **errp);
} AccelCPUClass; } AccelCPUClass;
#endif /* ACCEL_CPU_H */ #endif /* ACCEL_CPU_H */

2
include/qemu/accel.h
View File

@ -89,6 +89,6 @@ void accel_cpu_instance_init(CPUState *cpu);
* @cpu: The CPU that needs to call accel-specific cpu realization. * @cpu: The CPU that needs to call accel-specific cpu realization.
* @errp: currently unused. * @errp: currently unused.
*/ */
void accel_cpu_realizefn(CPUState *cpu, Error **errp); bool accel_cpu_realizefn(CPUState *cpu, Error **errp);
#endif /* QEMU_ACCEL_H */ #endif /* QEMU_ACCEL_H */

5
target/i386/host-cpu.c
View File

@ -80,7 +80,7 @@ static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu)
return phys_bits; return phys_bits;
} }
void host_cpu_realizefn(CPUState *cs, Error **errp) bool host_cpu_realizefn(CPUState *cs, Error **errp)
{ {
X86CPU *cpu = X86_CPU(cs); X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env; CPUX86State *env = &cpu->env;
@ -97,10 +97,11 @@ void host_cpu_realizefn(CPUState *cs, Error **errp)
error_setg(errp, "phys-bits should be between 32 and %u " error_setg(errp, "phys-bits should be between 32 and %u "
" (but is %u)", " (but is %u)",
TARGET_PHYS_ADDR_SPACE_BITS, phys_bits); TARGET_PHYS_ADDR_SPACE_BITS, phys_bits);
return; return false;
} }
cpu->phys_bits = phys_bits; cpu->phys_bits = phys_bits;
} }
return true;
} }
#define CPUID_MODEL_ID_SZ 48 #define CPUID_MODEL_ID_SZ 48

2
target/i386/host-cpu.h
View File

@ -12,7 +12,7 @@
void host_cpu_instance_init(X86CPU *cpu); void host_cpu_instance_init(X86CPU *cpu);
void host_cpu_max_instance_init(X86CPU *cpu); void host_cpu_max_instance_init(X86CPU *cpu);
void host_cpu_realizefn(CPUState *cs, Error **errp); bool host_cpu_realizefn(CPUState *cs, Error **errp);
void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepping); void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepping);

4
target/i386/kvm/kvm-cpu.c
View File

@ -18,7 +18,7 @@
#include "kvm_i386.h" #include "kvm_i386.h"
#include "hw/core/accel-cpu.h" #include "hw/core/accel-cpu.h"
static void kvm_cpu_realizefn(CPUState *cs, Error **errp) static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)
{ {
X86CPU *cpu = X86_CPU(cs); X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env; CPUX86State *env = &cpu->env;
@ -41,7 +41,7 @@ static void kvm_cpu_realizefn(CPUState *cs, Error **errp)
MSR_IA32_UCODE_REV); MSR_IA32_UCODE_REV);
} }
} }
host_cpu_realizefn(cs, errp); return host_cpu_realizefn(cs, errp);
} }
/* /*

6
target/i386/tcg/tcg-cpu.c
View File

@ -96,7 +96,7 @@ static void x86_cpu_machine_done(Notifier *n, void *unused)
} }
} }
static void tcg_cpu_realizefn(CPUState *cs, Error **errp) static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
{ {
X86CPU *cpu = X86_CPU(cs); X86CPU *cpu = X86_CPU(cs);
@ -132,12 +132,14 @@ static void tcg_cpu_realizefn(CPUState *cs, Error **errp)
/* ... SMRAM with higher priority, linked from /machine/smram. */ /* ... SMRAM with higher priority, linked from /machine/smram. */
cpu->machine_done.notify = x86_cpu_machine_done; cpu->machine_done.notify = x86_cpu_machine_done;
qemu_add_machine_init_done_notifier(&cpu->machine_done); qemu_add_machine_init_done_notifier(&cpu->machine_done);
return true;
} }
#else /* CONFIG_USER_ONLY */ #else /* CONFIG_USER_ONLY */
static void tcg_cpu_realizefn(CPUState *cs, Error **errp) static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
{ {
return true;
} }
#endif /* !CONFIG_USER_ONLY */ #endif /* !CONFIG_USER_ONLY */