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hw/pci: factor PCI reserve resources to a separate structure

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Factor "bus_reserve", "io_reserve", "mem_reserve", "pref32_reserve"
and "pref64_reserve" fields of the "GenPCIERootPort" structure out
to "PCIResReserve" structure, so that other PCI bridges can
reuse it to add resource reserve capability.

Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jing Liu 2018-08-21 11:18:06 +08:00 committed by Michael S. Tsirkin
parent db812c4073
commit 9e8993991e
3 changed files with 47 additions and 42 deletions
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33
hw/pci-bridge/gen_pcie_root_port.c
View File

@ -29,12 +29,8 @@ typedef struct GenPCIERootPort {
bool migrate_msix; bool migrate_msix;
/* additional resources to reserve on firmware init */ /* additional resources to reserve */
uint32_t bus_reserve; PCIResReserve res_reserve;
uint64_t io_reserve;
uint64_t mem_reserve;
uint64_t pref32_reserve;
uint64_t pref64_reserve;
} GenPCIERootPort; } GenPCIERootPort;
static uint8_t gen_rp_aer_vector(const PCIDevice *d) static uint8_t gen_rp_aer_vector(const PCIDevice *d)
@ -82,16 +78,15 @@ static void gen_rp_realize(DeviceState *dev, Error **errp)
return; return;
} }
int rc = pci_bridge_qemu_reserve_cap_init(d, 0, grp->bus_reserve, int rc = pci_bridge_qemu_reserve_cap_init(d, 0,
grp->io_reserve, grp->mem_reserve, grp->pref32_reserve, grp->res_reserve, errp);
grp->pref64_reserve, errp);
if (rc < 0) { if (rc < 0) {
rpc->parent_class.exit(d); rpc->parent_class.exit(d);
return; return;
} }
if (!grp->io_reserve) { if (!grp->res_reserve.io) {
pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND, pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND,
PCI_COMMAND_IO); PCI_COMMAND_IO);
d->wmask[PCI_IO_BASE] = 0; d->wmask[PCI_IO_BASE] = 0;
@ -117,12 +112,18 @@ static const VMStateDescription vmstate_rp_dev = {
}; };
static Property gen_rp_props[] = { static Property gen_rp_props[] = {
DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true), DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort,
DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, bus_reserve, -1), migrate_msix, true),
DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort, io_reserve, -1), DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort,
DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort, mem_reserve, -1), res_reserve.bus, -1),
DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort, pref32_reserve, -1), DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort,
DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, pref64_reserve, -1), res_reserve.io, -1),
DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort,
res_reserve.mem_non_pref, -1),
DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort,
res_reserve.mem_pref_32, -1),
DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,
res_reserve.mem_pref_64, -1),
DEFINE_PROP_END_OF_LIST() DEFINE_PROP_END_OF_LIST()
}; };

38
hw/pci/pci_bridge.c
View File

@ -411,38 +411,34 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
uint32_t bus_reserve, uint64_t io_reserve, PCIResReserve res_reserve, Error **errp)
uint64_t mem_non_pref_reserve,
uint64_t mem_pref_32_reserve,
uint64_t mem_pref_64_reserve,
Error **errp)
{ {
if (mem_pref_32_reserve != (uint64_t)-1 && if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
mem_pref_64_reserve != (uint64_t)-1) { res_reserve.mem_pref_64 != (uint64_t)-1) {
error_setg(errp, error_setg(errp,
"PCI resource reserve cap: PREF32 and PREF64 conflict"); "PCI resource reserve cap: PREF32 and PREF64 conflict");
return -EINVAL; return -EINVAL;
} }
if (mem_non_pref_reserve != (uint64_t)-1 && if (res_reserve.mem_non_pref != (uint64_t)-1 &&
mem_non_pref_reserve >= (1ULL << 32)) { res_reserve.mem_non_pref >= (1ULL << 32)) {
error_setg(errp, error_setg(errp,
"PCI resource reserve cap: mem-reserve must be less than 4G"); "PCI resource reserve cap: mem-reserve must be less than 4G");
return -EINVAL; return -EINVAL;
} }
if (mem_pref_32_reserve != (uint64_t)-1 && if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
mem_pref_32_reserve >= (1ULL << 32)) { res_reserve.mem_pref_32 >= (1ULL << 32)) {
error_setg(errp, error_setg(errp,
"PCI resource reserve cap: pref32-reserve must be less than 4G"); "PCI resource reserve cap: pref32-reserve must be less than 4G");
return -EINVAL; return -EINVAL;
} }
if (bus_reserve == (uint32_t)-1 && if (res_reserve.bus == (uint32_t)-1 &&
io_reserve == (uint64_t)-1 && res_reserve.io == (uint64_t)-1 &&
mem_non_pref_reserve == (uint64_t)-1 && res_reserve.mem_non_pref == (uint64_t)-1 &&
mem_pref_32_reserve == (uint64_t)-1 && res_reserve.mem_pref_32 == (uint64_t)-1 &&
mem_pref_64_reserve == (uint64_t)-1) { res_reserve.mem_pref_64 == (uint64_t)-1) {
return 0; return 0;
} }
@ -450,11 +446,11 @@ int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
PCIBridgeQemuCap cap = { PCIBridgeQemuCap cap = {
.len = cap_len, .len = cap_len,
.type = REDHAT_PCI_CAP_RESOURCE_RESERVE, .type = REDHAT_PCI_CAP_RESOURCE_RESERVE,
.bus_res = bus_reserve, .bus_res = res_reserve.bus,
.io = io_reserve, .io = res_reserve.io,
.mem = mem_non_pref_reserve, .mem = res_reserve.mem_non_pref,
.mem_pref_32 = mem_pref_32_reserve, .mem_pref_32 = res_reserve.mem_pref_32,
.mem_pref_64 = mem_pref_64_reserve .mem_pref_64 = res_reserve.mem_pref_64
}; };
int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,

18
include/hw/pci/pci_bridge.h
View File

@ -133,11 +133,19 @@ typedef struct PCIBridgeQemuCap {
#define REDHAT_PCI_CAP_RESOURCE_RESERVE 1 #define REDHAT_PCI_CAP_RESOURCE_RESERVE 1
/*
* PCI BUS/IO/MEM/PREFMEM additional resources recorded as a
* capability in PCI configuration space to reserve on firmware init.
*/
typedef struct PCIResReserve {
uint32_t bus;
uint64_t io;
uint64_t mem_non_pref;
uint64_t mem_pref_32;
uint64_t mem_pref_64;
} PCIResReserve;
int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
uint32_t bus_reserve, uint64_t io_reserve, PCIResReserve res_reserve, Error **errp);
uint64_t mem_non_pref_reserve,
uint64_t mem_pref_32_reserve,
uint64_t mem_pref_64_reserve,
Error **errp);
#endif /* QEMU_PCI_BRIDGE_H */ #endif /* QEMU_PCI_BRIDGE_H */