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target/arm: Calculate mask/base_mask in get_level1_table_address()

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In get_level1_table_address(), instead of using precalculated values
of mask and base_mask from the TCR struct, calculate them directly
(in the same way we currently do in vmsa_ttbcr_raw_write() to
populate the TCR struct fields).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220714132303.1287193-3-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-07-14 14:22:58 +01:00
parent dfce4aa8fe
commit 9e70e26c53
1 changed files with 9 additions and 5 deletions
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14
target/arm/ptw.c
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@ -315,20 +315,24 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
uint32_t *table, uint32_t address) uint32_t *table, uint32_t address)
{ {
/* Note that we can only get here for an AArch32 PL0/PL1 lookup */ /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
TCR *tcr = regime_tcr(env, mmu_idx); uint64_t tcr = regime_tcr_value(env, mmu_idx);
int maskshift = extract32(tcr, 0, 3);
uint32_t mask = ~(((uint32_t)0xffffffffu) >> maskshift);
uint32_t base_mask;
if (address & tcr->mask) { if (address & mask) {
if (tcr->raw_tcr & TTBCR_PD1) { if (tcr & TTBCR_PD1) {
/* Translation table walk disabled for TTBR1 */ /* Translation table walk disabled for TTBR1 */
return false; return false;
} }
*table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
} else { } else {
if (tcr->raw_tcr & TTBCR_PD0) { if (tcr & TTBCR_PD0) {
/* Translation table walk disabled for TTBR0 */ /* Translation table walk disabled for TTBR0 */
return false; return false;
} }
*table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; base_mask = ~((uint32_t)0x3fffu >> maskshift);
*table = regime_ttbr(env, mmu_idx, 0) & base_mask;
} }
*table |= (address >> 18) & 0x3ffc; *table |= (address >> 18) & 0x3ffc;
return true; return true;