target/ppc: Remove msr_hv macro
msr_hv macro hides the usage of env->msr, which is a bad behavior. Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220504210541.115256-20-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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@ -354,6 +354,12 @@ typedef enum {
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#define MSR_RI 1 /* Recoverable interrupt 1 */
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#define MSR_LE 0 /* Little-endian mode 1 hflags */
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#if defined(TARGET_PPC64)
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FIELD(MSR, HV, MSR_HV, 1)
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#define FIELD_EX64_HV(storage) FIELD_EX64(storage, MSR, HV)
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#else
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#define FIELD_EX64_HV(storage) 0
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#endif
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FIELD(MSR, TS, MSR_TS0, 2)
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FIELD(MSR, CM, MSR_CM, 1)
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FIELD(MSR, GS, MSR_GS, 1)
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@ -489,11 +495,6 @@ FIELD(MSR, LE, MSR_LE, 1)
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#define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */
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#define HFSCR_IC_MSGP 0xA
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#if defined(TARGET_PPC64)
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#define msr_hv ((env->msr >> MSR_HV) & 1)
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#else
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#define msr_hv (0)
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#endif
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#define msr_de ((env->msr >> MSR_DE) & 1)
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#define DBCR0_ICMP (1 << 27)
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@ -6305,7 +6305,8 @@ static bool cpu_has_work_POWER9(CPUState *cs)
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if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
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(env->spr[SPR_LPCR] & LPCR_EEE)) {
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bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
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if (!heic || !msr_hv || FIELD_EX64(env->msr, MSR, PR)) {
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if (!heic || !FIELD_EX64_HV(env->msr) ||
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FIELD_EX64(env->msr, MSR, PR)) {
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return true;
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}
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}
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@ -6520,7 +6521,8 @@ static bool cpu_has_work_POWER10(CPUState *cs)
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if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
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(env->spr[SPR_LPCR] & LPCR_EEE)) {
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bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
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if (!heic || !msr_hv || FIELD_EX64(env->msr, MSR, PR)) {
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if (!heic || !FIELD_EX64_HV(env->msr) ||
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FIELD_EX64(env->msr, MSR, PR)) {
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return true;
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}
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}
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@ -1715,7 +1715,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
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if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
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/* LPCR will be clear when not supported so this will work */
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bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
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if ((async_deliver || msr_hv == 0) && hdice) {
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if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) {
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/* HDEC clears on delivery */
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env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
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powerpc_excp(cpu, POWERPC_EXCP_HDECR);
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@ -1727,7 +1727,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
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if (env->pending_interrupts & (1 << PPC_INTERRUPT_HVIRT)) {
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/* LPCR will be clear when not supported so this will work */
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bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE);
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if ((async_deliver || msr_hv == 0) && hvice) {
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if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) {
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powerpc_excp(cpu, POWERPC_EXCP_HVIRT);
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return;
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}
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@ -1738,9 +1738,9 @@ static void ppc_hw_interrupt(CPUPPCState *env)
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bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
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bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
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/* HEIC blocks delivery to the hypervisor */
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if ((async_deliver && !(heic && msr_hv &&
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if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) &&
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!FIELD_EX64(env->msr, MSR, PR))) ||
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(env->has_hv_mode && msr_hv == 0 && !lpes0)) {
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(env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) {
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if (books_vhyp_promotes_external_to_hvirt(cpu)) {
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powerpc_excp(cpu, POWERPC_EXCP_HVIRT);
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} else {
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@ -612,11 +612,11 @@ void helper_tbegin(CPUPPCState *env)
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env->spr[SPR_TEXASR] =
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(1ULL << TEXASR_FAILURE_PERSISTENT) |
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(1ULL << TEXASR_NESTING_OVERFLOW) |
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(msr_hv << TEXASR_PRIVILEGE_HV) |
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(FIELD_EX64_HV(env->msr) << TEXASR_PRIVILEGE_HV) |
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(FIELD_EX64(env->msr, MSR, PR) << TEXASR_PRIVILEGE_PR) |
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(1ULL << TEXASR_FAILURE_SUMMARY) |
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(1ULL << TEXASR_TFIAR_EXACT);
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env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) |
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env->spr[SPR_TFIAR] = env->nip | (FIELD_EX64_HV(env->msr) << 1) |
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FIELD_EX64(env->msr, MSR, PR);
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env->spr[SPR_TFHAR] = env->nip + 4;
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env->crf[0] = 0xB; /* 0b1010 = transaction failure */
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@ -73,7 +73,7 @@ void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
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const char *caller, uint32_t cause)
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{
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#ifdef TARGET_PPC64
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if ((env->msr_mask & MSR_HVB) && !msr_hv &&
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if ((env->msr_mask & MSR_HVB) && !FIELD_EX64(env->msr, MSR, HV) &&
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!(env->spr[SPR_HFSCR] & (1UL << bit))) {
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raise_hv_fu_exception(env, bit, caller, cause, GETPC());
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}
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@ -37,7 +37,7 @@ static bool ppc_radix64_get_fully_qualified_addr(const CPUPPCState *env,
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return false;
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}
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if (msr_hv) { /* MSR[HV] -> Hypervisor/bare metal */
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if (FIELD_EX64(env->msr, MSR, HV)) { /* MSR[HV] -> Hypervisor/bare metal */
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switch (eaddr & R_EADDR_QUADRANT) {
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case R_EADDR_QUADRANT0:
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*lpid = 0;
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@ -306,7 +306,7 @@ static bool validate_pate(PowerPCCPU *cpu, uint64_t lpid, ppc_v3_pate_t *pate)
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if (!(pate->dw0 & PATE0_HR)) {
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return false;
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}
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if (lpid == 0 && !msr_hv) {
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if (lpid == 0 && !FIELD_EX64(env->msr, MSR, HV)) {
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return false;
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}
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if ((pate->dw0 & PATE1_R_PRTS) < 5) {
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@ -431,7 +431,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
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*g_page_size = PRTBE_R_GET_RTS(prtbe0);
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base_addr = prtbe0 & PRTBE_R_RPDB;
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nls = prtbe0 & PRTBE_R_RPDS;
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if (msr_hv || vhyp_flat_addressing(cpu)) {
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if (FIELD_EX64(env->msr, MSR, HV) || vhyp_flat_addressing(cpu)) {
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/*
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* Can treat process table addresses as real addresses
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*/
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