target/nios2: Use hw/registerfields.h for CR_TLBACC fields
Retain the helper macros for single bit fields as aliases to the longer R_*_MASK names. Use FIELD_EX32 and FIELD_DP32 instead of manually manipulating the fields. Since we're rewriting the references to CR_TLBACC_IGN_* anyway, we correct the name of this field to IG, which is its name in the official CPU documentation. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-28-richard.henderson@linaro.org>
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@ -115,14 +115,21 @@ FIELD(CR_PTEADDR, VPN, 2, 20)
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FIELD(CR_PTEADDR, PTBASE, 22, 10)
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#define CR_TLBACC 9
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#define CR_TLBACC_IGN_SHIFT 25
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#define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT)
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#define CR_TLBACC_C (1 << 24)
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#define CR_TLBACC_R (1 << 23)
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#define CR_TLBACC_W (1 << 22)
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#define CR_TLBACC_X (1 << 21)
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#define CR_TLBACC_G (1 << 20)
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#define CR_TLBACC_PFN_MASK 0x000FFFFF
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FIELD(CR_TLBACC, PFN, 0, 20)
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FIELD(CR_TLBACC, G, 20, 1)
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FIELD(CR_TLBACC, X, 21, 1)
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FIELD(CR_TLBACC, W, 22, 1)
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FIELD(CR_TLBACC, R, 23, 1)
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FIELD(CR_TLBACC, C, 24, 1)
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FIELD(CR_TLBACC, IG, 25, 7)
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#define CR_TLBACC_C R_CR_TLBACC_C_MASK
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#define CR_TLBACC_R R_CR_TLBACC_R_MASK
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#define CR_TLBACC_W R_CR_TLBACC_W_MASK
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#define CR_TLBACC_X R_CR_TLBACC_X_MASK
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#define CR_TLBACC_G R_CR_TLBACC_G_MASK
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#define CR_TLBMISC 10
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#define CR_TLBMISC_WAY_SHIFT 20
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#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT)
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@ -49,7 +49,7 @@ unsigned int mmu_translate(CPUNios2State *env,
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}
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lu->vaddr = vaddr & TARGET_PAGE_MASK;
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lu->paddr = (entry->data & CR_TLBACC_PFN_MASK) << TARGET_PAGE_BITS;
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lu->paddr = FIELD_EX32(entry->data, CR_TLBACC, PFN) << TARGET_PAGE_BITS;
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lu->prot = ((entry->data & CR_TLBACC_R) ? PAGE_READ : 0) |
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((entry->data & CR_TLBACC_W) ? PAGE_WRITE : 0) |
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((entry->data & CR_TLBACC_X) ? PAGE_EXEC : 0);
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@ -86,27 +86,27 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
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CPUState *cs = env_cpu(env);
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Nios2CPU *cpu = env_archcpu(env);
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trace_nios2_mmu_write_tlbacc(v >> CR_TLBACC_IGN_SHIFT,
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trace_nios2_mmu_write_tlbacc(FIELD_EX32(v, CR_TLBACC, IG),
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(v & CR_TLBACC_C) ? 'C' : '.',
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(v & CR_TLBACC_R) ? 'R' : '.',
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(v & CR_TLBACC_W) ? 'W' : '.',
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(v & CR_TLBACC_X) ? 'X' : '.',
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(v & CR_TLBACC_G) ? 'G' : '.',
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v & CR_TLBACC_PFN_MASK);
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FIELD_EX32(v, CR_TLBACC, PFN));
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/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
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if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) {
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int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT);
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int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
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int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
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int g = (v & CR_TLBACC_G) ? 1 : 0;
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int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0;
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int g = FIELD_EX32(v, CR_TLBACC, G);
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int valid = FIELD_EX32(vpn, CR_TLBACC, PFN) < 0xC0000;
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Nios2TLBEntry *entry =
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&env->mmu.tlb[(way * cpu->tlb_num_ways) +
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(vpn & env->mmu.tlb_entry_mask)];
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uint32_t newTag = (vpn << 12) | (g << 11) | (valid << 10) | pid;
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uint32_t newData = v & (CR_TLBACC_C | CR_TLBACC_R | CR_TLBACC_W |
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CR_TLBACC_X | CR_TLBACC_PFN_MASK);
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CR_TLBACC_X | R_CR_TLBACC_PFN_MASK);
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if ((entry->tag != newTag) || (entry->data != newData)) {
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if (entry->tag & (1 << 10)) {
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@ -153,7 +153,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
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&env->mmu.tlb[(way * cpu->tlb_num_ways) +
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(vpn & env->mmu.tlb_entry_mask)];
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env->ctrl[CR_TLBACC] &= CR_TLBACC_IGN_MASK;
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env->ctrl[CR_TLBACC] &= R_CR_TLBACC_IG_MASK;
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env->ctrl[CR_TLBACC] |= entry->data;
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env->ctrl[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0;
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env->ctrl[CR_TLBMISC] =
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@ -208,7 +208,7 @@ void dump_mmu(CPUNios2State *env)
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entry->tag >> 12,
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entry->tag & ((1 << cpu->pid_num_bits) - 1),
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(entry->tag & (1 << 11)) ? 'G' : '-',
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entry->data & CR_TLBACC_PFN_MASK,
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FIELD_EX32(entry->data, CR_TLBACC, PFN),
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(entry->data & CR_TLBACC_C) ? 'C' : '-',
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(entry->data & CR_TLBACC_R) ? 'R' : '-',
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(entry->data & CR_TLBACC_W) ? 'W' : '-',
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