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target/riscv: move 'elen' to riscv_cpu_properties[]

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Do the same thing we did with 'vlen' in the previous patch with 'elen'.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Message-ID: <20240105230546.265053-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2024-01-05 20:05:38 -03:00 committed by Alistair Francis
parent fae0b53360
commit 9d1173d20d
2 changed files with 42 additions and 7 deletions
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44
target/riscv/cpu.c
View File

@ -1319,6 +1319,7 @@ static void riscv_cpu_init(Object *obj)
/* Default values for non-bool cpu properties */
cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, 16);
cpu->cfg.vlen = 128;
cpu->cfg.elen = 64;
cpu->env.vext_ver = VEXT_VERSION_1_00_0;
}
@ -1830,9 +1831,47 @@ static const PropertyInfo prop_vlen = {
.set = prop_vlen_set,
};
Property riscv_cpu_options[] = {
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
static void prop_elen_set(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
RISCVCPU *cpu = RISCV_CPU(obj);
uint16_t value;
if (!visit_type_uint16(v, name, &value, errp)) {
return;
}
if (!is_power_of_2(value)) {
error_setg(errp, "Vector extension ELEN must be power of 2");
return;
}
if (value != cpu->cfg.elen && riscv_cpu_is_vendor(obj)) {
cpu_set_prop_err(cpu, name, errp);
error_append_hint(errp, "Current '%s' val: %u\n",
name, cpu->cfg.elen);
return;
}
cpu_option_add_user_setting(name, value);
cpu->cfg.elen = value;
}
static void prop_elen_get(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
uint16_t value = RISCV_CPU(obj)->cfg.elen;
visit_type_uint16(v, name, &value, errp);
}
static const PropertyInfo prop_elen = {
.name = "elen",
.get = prop_elen_get,
.set = prop_elen_set,
};
Property riscv_cpu_options[] = {
DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
DEFINE_PROP_UINT16("cbop_blocksize", RISCVCPU, cfg.cbop_blocksize, 64),
DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
@ -1920,6 +1959,7 @@ static Property riscv_cpu_properties[] = {
{.name = "vext_spec", .info = &prop_vext_spec},
{.name = "vlen", .info = &prop_vlen},
{.name = "elen", .info = &prop_elen},
#ifndef CONFIG_USER_ONLY
DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),

5
target/riscv/tcg/tcg-cpu.c
View File

@ -305,11 +305,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
return;
}
if (!is_power_of_2(cfg->elen)) {
error_setg(errp, "Vector extension ELEN must be power of 2");
return;
}
if (cfg->elen > 64 || cfg->elen < 8) {
error_setg(errp,
"Vector extension implementation only supports ELEN "