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target/arm: Convert handle_scalar_simd_shri to decodetree

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This includes SSHR, USHR, SSRA, USRA, SRSHR, URSHR,
SRSRA, URSRA, SRI.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240912024114.1097832-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-09-11 19:41:08 -07:00 committed by Peter Maydell
parent fe5b8abe17
commit 9c80de4884
2 changed files with 86 additions and 70 deletions
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16
target/arm/tcg/a64.decode
View File

@ -30,6 +30,7 @@
&rri_sf rd rn imm sf
&i imm
&rr_e rd rn esz
&rri_e rd rn imm esz
&rrr_e rd rn rm esz
&rrx_e rd rn rm idx esz
&rrrr_e rd rn rm ra esz
@ -1285,3 +1286,18 @@ SHRN_v 0.00 11110 .... ... 10000 1 ..... ..... @q_shri_s
RSHRN_v 0.00 11110 .... ... 10001 1 ..... ..... @q_shri_b
RSHRN_v 0.00 11110 .... ... 10001 1 ..... ..... @q_shri_h
RSHRN_v 0.00 11110 .... ... 10001 1 ..... ..... @q_shri_s
# Advanced SIMD scalar shift by immediate
@shri_d .... ..... 1 ...... ..... . rn:5 rd:5 \
&rri_e esz=3 imm=%neon_rshift_i6
SSHR_s 0101 11110 .... ... 00000 1 ..... ..... @shri_d
USHR_s 0111 11110 .... ... 00000 1 ..... ..... @shri_d
SSRA_s 0101 11110 .... ... 00010 1 ..... ..... @shri_d
USRA_s 0111 11110 .... ... 00010 1 ..... ..... @shri_d
SRSHR_s 0101 11110 .... ... 00100 1 ..... ..... @shri_d
URSHR_s 0111 11110 .... ... 00100 1 ..... ..... @shri_d
SRSRA_s 0101 11110 .... ... 00110 1 ..... ..... @shri_d
URSRA_s 0111 11110 .... ... 00110 1 ..... ..... @shri_d
SRI_s 0111 11110 .... ... 01000 1 ..... ..... @shri_d

140
target/arm/tcg/translate-a64.c
View File

@ -7035,6 +7035,18 @@ static void gen_ushr_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift)
}
}
static void gen_ssra_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift)
{
gen_sshr_d(src, src, shift);
tcg_gen_add_i64(dst, dst, src);
}
static void gen_usra_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift)
{
gen_ushr_d(src, src, shift);
tcg_gen_add_i64(dst, dst, src);
}
static void gen_srshr_bhs(TCGv_i64 dst, TCGv_i64 src, int64_t shift)
{
assert(shift >= 0 && shift <= 32);
@ -7091,6 +7103,27 @@ static void gen_urshr_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift)
}
}
static void gen_srsra_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift)
{
gen_srshr_d(src, src, shift);
tcg_gen_add_i64(dst, dst, src);
}
static void gen_ursra_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift)
{
gen_urshr_d(src, src, shift);
tcg_gen_add_i64(dst, dst, src);
}
static void gen_sri_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift)
{
/* If shift is 64, dst is unchanged. */
if (shift != 64) {
tcg_gen_shri_i64(src, src, shift);
tcg_gen_deposit_i64(dst, dst, src, 0, 64 - shift);
}
}
static bool do_vec_shift_imm_narrow(DisasContext *s, arg_qrri_e *a,
WideShiftImmFn * const fns[3], MemOp sign)
{
@ -7136,6 +7169,38 @@ static WideShiftImmFn * const rshrn_fns[] = {
};
TRANS(RSHRN_v, do_vec_shift_imm_narrow, a, rshrn_fns, 0)
/*
* Advanced SIMD Scalar Shift by Immediate
*/
static bool do_scalar_shift_imm(DisasContext *s, arg_rri_e *a,
WideShiftImmFn *fn, bool accumulate,
MemOp sign)
{
if (fp_access_check(s)) {
TCGv_i64 rd = tcg_temp_new_i64();
TCGv_i64 rn = tcg_temp_new_i64();
read_vec_element(s, rn, a->rn, 0, a->esz | sign);
if (accumulate) {
read_vec_element(s, rd, a->rd, 0, a->esz | sign);
}
fn(rd, rn, a->imm);
write_fp_dreg(s, a->rd, rd);
}
return true;
}
TRANS(SSHR_s, do_scalar_shift_imm, a, gen_sshr_d, false, 0)
TRANS(USHR_s, do_scalar_shift_imm, a, gen_ushr_d, false, 0)
TRANS(SSRA_s, do_scalar_shift_imm, a, gen_ssra_d, true, 0)
TRANS(USRA_s, do_scalar_shift_imm, a, gen_usra_d, true, 0)
TRANS(SRSHR_s, do_scalar_shift_imm, a, gen_srshr_d, false, 0)
TRANS(URSHR_s, do_scalar_shift_imm, a, gen_urshr_d, false, 0)
TRANS(SRSRA_s, do_scalar_shift_imm, a, gen_srsra_d, true, 0)
TRANS(URSRA_s, do_scalar_shift_imm, a, gen_ursra_d, true, 0)
TRANS(SRI_s, do_scalar_shift_imm, a, gen_sri_d, true, 0)
/* Shift a TCGv src by TCGv shift_amount, put result in dst.
* Note that it is the caller's responsibility to ensure that the
* shift amount is in range (ie 0..31 or 0..63) and provide the ARM
@ -9352,64 +9417,6 @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
}
}
/* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
static void handle_scalar_simd_shri(DisasContext *s,
bool is_u, int immh, int immb,
int opcode, int rn, int rd)
{
const int size = 3;
int immhb = immh << 3 | immb;
int shift = 2 * (8 << size) - immhb;
bool accumulate = false;
bool round = false;
bool insert = false;
TCGv_i64 tcg_rn;
TCGv_i64 tcg_rd;
if (!extract32(immh, 3, 1)) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
switch (opcode) {
case 0x02: /* SSRA / USRA (accumulate) */
accumulate = true;
break;
case 0x04: /* SRSHR / URSHR (rounding) */
round = true;
break;
case 0x06: /* SRSRA / URSRA (accum + rounding) */
accumulate = round = true;
break;
case 0x08: /* SRI */
insert = true;
break;
}
tcg_rn = read_fp_dreg(s, rn);
tcg_rd = (accumulate || insert) ? read_fp_dreg(s, rd) : tcg_temp_new_i64();
if (insert) {
/* shift count same as element size is valid but does nothing;
* special case to avoid potential shift by 64.
*/
int esize = 8 << size;
if (shift != esize) {
tcg_gen_shri_i64(tcg_rn, tcg_rn, shift);
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, 0, esize - shift);
}
} else {
handle_shri_with_rndacc(tcg_rd, tcg_rn, round,
accumulate, is_u, size, shift);
}
write_fp_dreg(s, rd, tcg_rd);
}
/* SHL/SLI - Scalar shift left */
static void handle_scalar_simd_shli(DisasContext *s, bool insert,
int immh, int immb, int opcode,
@ -9893,18 +9900,6 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
}
switch (opcode) {
case 0x08: /* SRI */
if (!is_u) {
unallocated_encoding(s);
return;
}
/* fall through */
case 0x00: /* SSHR / USHR */
case 0x02: /* SSRA / USRA */
case 0x04: /* SRSHR / URSHR */
case 0x06: /* SRSRA / URSRA */
handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd);
break;
case 0x0a: /* SHL / SLI */
handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd);
break;
@ -9940,6 +9935,11 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd);
break;
default:
case 0x00: /* SSHR / USHR */
case 0x02: /* SSRA / USRA */
case 0x04: /* SRSHR / URSHR */
case 0x06: /* SRSRA / URSRA */
case 0x08: /* SRI */
unallocated_encoding(s);
break;
}