tcg: Pass generic CPUState to gen_intermediate_code()
Needed to implement a target-agnostic gen_intermediate_code() in the future. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
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797ed66d29
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@ -1280,7 +1280,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
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tcg_func_start(&tcg_ctx);
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tcg_func_start(&tcg_ctx);
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tcg_ctx.cpu = ENV_GET_CPU(env);
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tcg_ctx.cpu = ENV_GET_CPU(env);
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gen_intermediate_code(env, tb);
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gen_intermediate_code(cpu, tb);
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tcg_ctx.cpu = NULL;
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tcg_ctx.cpu = NULL;
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trace_translate_block(tb, tb->pc, tb->tc_ptr);
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trace_translate_block(tb, tb->pc, tb->tc_ptr);
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@ -66,7 +66,7 @@ typedef ram_addr_t tb_page_addr_t;
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#include "qemu/log.h"
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#include "qemu/log.h"
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void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
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void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb);
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void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
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void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
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target_ulong *data);
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target_ulong *data);
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@ -2952,10 +2952,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
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return ret;
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return ret;
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}
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}
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void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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{
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{
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AlphaCPU *cpu = alpha_env_get_cpu(env);
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CPUAlphaState *env = cs->env_ptr;
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CPUState *cs = CPU(cpu);
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DisasContext ctx, *ctxp = &ctx;
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DisasContext ctx, *ctxp = &ctx;
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target_ulong pc_start;
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target_ulong pc_start;
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target_ulong pc_mask;
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target_ulong pc_mask;
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@ -11179,10 +11179,10 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
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free_tmp_a64(s);
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free_tmp_a64(s);
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}
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}
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void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
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void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)
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{
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{
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CPUState *cs = CPU(cpu);
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CPUARMState *env = cs->env_ptr;
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CPUARMState *env = &cpu->env;
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ARMCPU *cpu = arm_env_get_cpu(env);
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DisasContext dc1, *dc = &dc1;
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DisasContext dc1, *dc = &dc1;
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target_ulong pc_start;
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target_ulong pc_start;
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target_ulong next_page_start;
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target_ulong next_page_start;
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@ -11795,10 +11795,10 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
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}
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}
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/* generate intermediate code for basic block 'tb'. */
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/* generate intermediate code for basic block 'tb'. */
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void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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{
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{
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CPUARMState *env = cs->env_ptr;
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ARMCPU *cpu = arm_env_get_cpu(env);
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ARMCPU *cpu = arm_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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DisasContext dc1, *dc = &dc1;
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DisasContext dc1, *dc = &dc1;
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target_ulong pc_start;
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target_ulong pc_start;
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target_ulong next_page_start;
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target_ulong next_page_start;
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@ -11812,7 +11812,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
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* the A32/T32 complexity to do with conditional execution/IT blocks/etc.
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* the A32/T32 complexity to do with conditional execution/IT blocks/etc.
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*/
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*/
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if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
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if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
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gen_intermediate_code_a64(cpu, tb);
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gen_intermediate_code_a64(cs, tb);
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return;
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return;
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}
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}
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@ -149,7 +149,7 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
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#ifdef TARGET_AARCH64
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#ifdef TARGET_AARCH64
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void a64_translate_init(void);
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void a64_translate_init(void);
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void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb);
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void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb);
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void gen_a64_set_pc_im(uint64_t val);
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void gen_a64_set_pc_im(uint64_t val);
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void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
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void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
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fprintf_function cpu_fprintf, int flags);
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fprintf_function cpu_fprintf, int flags);
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@ -158,7 +158,7 @@ static inline void a64_translate_init(void)
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{
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{
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}
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}
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static inline void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
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static inline void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb)
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{
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{
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}
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}
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@ -3080,10 +3080,9 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
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*/
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*/
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/* generate intermediate code for basic block 'tb'. */
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/* generate intermediate code for basic block 'tb'. */
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void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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{
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{
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CRISCPU *cpu = cris_env_get_cpu(env);
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CPUCRISState *env = cs->env_ptr;
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CPUState *cs = CPU(cpu);
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uint32_t pc_start;
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uint32_t pc_start;
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unsigned int insn_len;
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unsigned int insn_len;
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struct DisasContext ctx;
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struct DisasContext ctx;
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@ -3105,7 +3104,7 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
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* delayslot, like in real hw.
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* delayslot, like in real hw.
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*/
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*/
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pc_start = tb->pc & ~1;
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pc_start = tb->pc & ~1;
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dc->cpu = cpu;
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dc->cpu = cris_env_get_cpu(env);
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dc->tb = tb;
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dc->tb = tb;
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dc->is_jmp = DISAS_NEXT;
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dc->is_jmp = DISAS_NEXT;
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@ -3740,10 +3740,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
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return gen_illegal(ctx);
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return gen_illegal(ctx);
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}
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}
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void gen_intermediate_code(CPUHPPAState *env, struct TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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{
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{
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HPPACPU *cpu = hppa_env_get_cpu(env);
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CPUHPPAState *env = cs->env_ptr;
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CPUState *cs = CPU(cpu);
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DisasContext ctx;
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DisasContext ctx;
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ExitStatus ret;
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ExitStatus ret;
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int num_insns, max_insns, i;
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int num_insns, max_insns, i;
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@ -8378,10 +8378,9 @@ void tcg_x86_init(void)
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}
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}
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/* generate intermediate code for basic block 'tb'. */
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/* generate intermediate code for basic block 'tb'. */
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void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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{
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{
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X86CPU *cpu = x86_env_get_cpu(env);
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CPUX86State *env = cs->env_ptr;
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CPUState *cs = CPU(cpu);
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DisasContext dc1, *dc = &dc1;
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DisasContext dc1, *dc = &dc1;
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target_ulong pc_ptr;
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target_ulong pc_ptr;
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uint32_t flags;
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uint32_t flags;
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@ -1044,10 +1044,10 @@ static inline void decode(DisasContext *dc, uint32_t ir)
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}
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}
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/* generate intermediate code for basic block 'tb'. */
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/* generate intermediate code for basic block 'tb'. */
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void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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{
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{
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CPULM32State *env = cs->env_ptr;
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LM32CPU *cpu = lm32_env_get_cpu(env);
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LM32CPU *cpu = lm32_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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struct DisasContext ctx, *dc = &ctx;
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struct DisasContext ctx, *dc = &ctx;
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uint32_t pc_start;
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uint32_t pc_start;
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uint32_t next_page_start;
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uint32_t next_page_start;
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@ -5518,10 +5518,9 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
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}
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}
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/* generate intermediate code for basic block 'tb'. */
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/* generate intermediate code for basic block 'tb'. */
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void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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{
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{
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M68kCPU *cpu = m68k_env_get_cpu(env);
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CPUM68KState *env = cs->env_ptr;
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CPUState *cs = CPU(cpu);
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DisasContext dc1, *dc = &dc1;
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DisasContext dc1, *dc = &dc1;
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target_ulong pc_start;
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target_ulong pc_start;
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int pc_offset;
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int pc_offset;
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@ -1625,10 +1625,10 @@ static inline void decode(DisasContext *dc, uint32_t ir)
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}
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}
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/* generate intermediate code for basic block 'tb'. */
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/* generate intermediate code for basic block 'tb'. */
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void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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{
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{
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CPUMBState *env = cs->env_ptr;
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MicroBlazeCPU *cpu = mb_env_get_cpu(env);
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MicroBlazeCPU *cpu = mb_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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uint32_t pc_start;
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uint32_t pc_start;
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struct DisasContext ctx;
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struct DisasContext ctx;
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struct DisasContext *dc = &ctx;
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struct DisasContext *dc = &ctx;
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@ -19888,10 +19888,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
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}
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}
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}
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}
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void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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{
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{
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MIPSCPU *cpu = mips_env_get_cpu(env);
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CPUMIPSState *env = cs->env_ptr;
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CPUState *cs = CPU(cpu);
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DisasContext ctx;
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DisasContext ctx;
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target_ulong pc_start;
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target_ulong pc_start;
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target_ulong next_page_start;
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target_ulong next_page_start;
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@ -822,10 +822,10 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
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}
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}
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/* generate intermediate code for basic block 'tb'. */
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/* generate intermediate code for basic block 'tb'. */
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void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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{
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{
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CPUMoxieState *env = cs->env_ptr;
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MoxieCPU *cpu = moxie_env_get_cpu(env);
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MoxieCPU *cpu = moxie_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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DisasContext ctx;
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DisasContext ctx;
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target_ulong pc_start;
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target_ulong pc_start;
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int num_insns, max_insns;
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int num_insns, max_insns;
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@ -799,10 +799,9 @@ static void gen_exception(DisasContext *dc, uint32_t excp)
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}
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}
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/* generate intermediate code for basic block 'tb'. */
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/* generate intermediate code for basic block 'tb'. */
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void gen_intermediate_code(CPUNios2State *env, TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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{
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{
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Nios2CPU *cpu = nios2_env_get_cpu(env);
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CPUNios2State *env = cs->env_ptr;
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CPUState *cs = CPU(cpu);
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DisasContext dc1, *dc = &dc1;
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DisasContext dc1, *dc = &dc1;
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int num_insns;
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int num_insns;
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int max_insns;
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int max_insns;
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@ -1518,10 +1518,10 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
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}
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}
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}
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}
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void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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{
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{
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CPUOpenRISCState *env = cs->env_ptr;
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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struct DisasContext ctx, *dc = &ctx;
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struct DisasContext ctx, *dc = &ctx;
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uint32_t pc_start;
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uint32_t pc_start;
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uint32_t next_page_start;
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uint32_t next_page_start;
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@ -7196,10 +7196,9 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
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}
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}
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/*****************************************************************************/
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/*****************************************************************************/
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void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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{
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{
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PowerPCCPU *cpu = ppc_env_get_cpu(env);
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CPUPPCState *env = cs->env_ptr;
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CPUState *cs = CPU(cpu);
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DisasContext ctx, *ctxp = &ctx;
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DisasContext ctx, *ctxp = &ctx;
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opc_handler_t **table, *handler;
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opc_handler_t **table, *handler;
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target_ulong pc_start;
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target_ulong pc_start;
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@ -5853,10 +5853,9 @@ static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
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return ret;
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return ret;
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}
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}
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void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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{
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{
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S390CPU *cpu = s390_env_get_cpu(env);
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CPUS390XState *env = cs->env_ptr;
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CPUState *cs = CPU(cpu);
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DisasContext dc;
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DisasContext dc;
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target_ulong pc_start;
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target_ulong pc_start;
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uint64_t next_page_start;
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uint64_t next_page_start;
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@ -2230,10 +2230,9 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)
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}
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}
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#endif
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#endif
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void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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{
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{
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SuperHCPU *cpu = sh_env_get_cpu(env);
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CPUSH4State *env = cs->env_ptr;
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CPUState *cs = CPU(cpu);
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DisasContext ctx;
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DisasContext ctx;
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target_ulong pc_start;
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target_ulong pc_start;
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int num_insns;
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int num_insns;
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@ -5739,10 +5739,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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}
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}
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}
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}
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void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
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void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
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{
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{
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SPARCCPU *cpu = sparc_env_get_cpu(env);
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CPUSPARCState *env = cs->env_ptr;
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CPUState *cs = CPU(cpu);
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target_ulong pc_start, last_pc;
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target_ulong pc_start, last_pc;
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DisasContext dc1, *dc = &dc1;
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DisasContext dc1, *dc = &dc1;
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int num_insns;
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int num_insns;
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@ -2370,12 +2370,11 @@ static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
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}
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}
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}
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}
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void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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{
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{
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TileGXCPU *cpu = tilegx_env_get_cpu(env);
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CPUTLGState *env = cs->env_ptr;
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DisasContext ctx;
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DisasContext ctx;
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DisasContext *dc = &ctx;
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DisasContext *dc = &ctx;
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CPUState *cs = CPU(cpu);
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uint64_t pc_start = tb->pc;
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uint64_t pc_start = tb->pc;
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uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
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uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
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int num_insns = 0;
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int num_insns = 0;
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@ -8782,10 +8782,9 @@ static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
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|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
|
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
|
||||||
{
|
{
|
||||||
TriCoreCPU *cpu = tricore_env_get_cpu(env);
|
CPUTriCoreState *env = cs->env_ptr;
|
||||||
CPUState *cs = CPU(cpu);
|
|
||||||
DisasContext ctx;
|
DisasContext ctx;
|
||||||
target_ulong pc_start;
|
target_ulong pc_start;
|
||||||
int num_insns, max_insns;
|
int num_insns, max_insns;
|
||||||
|
@ -1869,10 +1869,9 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/* generate intermediate code for basic block 'tb'. */
|
/* generate intermediate code for basic block 'tb'. */
|
||||||
void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
|
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
|
||||||
{
|
{
|
||||||
UniCore32CPU *cpu = uc32_env_get_cpu(env);
|
CPUUniCore32State *env = cs->env_ptr;
|
||||||
CPUState *cs = CPU(cpu);
|
|
||||||
DisasContext dc1, *dc = &dc1;
|
DisasContext dc1, *dc = &dc1;
|
||||||
target_ulong pc_start;
|
target_ulong pc_start;
|
||||||
uint32_t next_page_start;
|
uint32_t next_page_start;
|
||||||
|
@ -3117,10 +3117,9 @@ static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
|
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
|
||||||
{
|
{
|
||||||
XtensaCPU *cpu = xtensa_env_get_cpu(env);
|
CPUXtensaState *env = cs->env_ptr;
|
||||||
CPUState *cs = CPU(cpu);
|
|
||||||
DisasContext dc;
|
DisasContext dc;
|
||||||
int insn_count = 0;
|
int insn_count = 0;
|
||||||
int max_insns = tb->cflags & CF_COUNT_MASK;
|
int max_insns = tb->cflags & CF_COUNT_MASK;
|
||||||
|
Loading…
Reference in New Issue
Block a user