target/sparc: Add TLB entry with attributes
Append MemTxAttrs to interfaces so we can pass along up coming Invert Endian TTE bit on SPARC64. Signed-off-by: Tony Nguyen <tony.nguyen@bt.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <f8fcc3138570c460ef289a6b34ba7715ba36f99e.1566466906.git.tony.nguyen@bt.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -88,7 +88,7 @@ static const int perm_table[2][8] = {
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};
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static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
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int *prot, int *access_index,
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int *prot, int *access_index, MemTxAttrs *attrs,
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target_ulong address, int rw, int mmu_idx,
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target_ulong *page_size)
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{
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@ -219,6 +219,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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target_ulong vaddr;
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target_ulong page_size;
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int error_code = 0, prot, access_index;
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MemTxAttrs attrs = {};
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/*
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* TODO: If we ever need tlb_vaddr_to_host for this target,
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@ -229,7 +230,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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assert(!probe);
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address &= TARGET_PAGE_MASK;
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error_code = get_physical_address(env, &paddr, &prot, &access_index,
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error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs,
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address, access_type,
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mmu_idx, &page_size);
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vaddr = address;
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@ -490,8 +491,8 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
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return 0;
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}
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static int get_physical_address_data(CPUSPARCState *env,
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hwaddr *physical, int *prot,
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static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
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int *prot, MemTxAttrs *attrs,
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target_ulong address, int rw, int mmu_idx)
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{
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CPUState *cs = env_cpu(env);
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@ -608,8 +609,8 @@ static int get_physical_address_data(CPUSPARCState *env,
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return 1;
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}
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static int get_physical_address_code(CPUSPARCState *env,
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hwaddr *physical, int *prot,
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static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,
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int *prot, MemTxAttrs *attrs,
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target_ulong address, int mmu_idx)
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{
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CPUState *cs = env_cpu(env);
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@ -686,7 +687,7 @@ static int get_physical_address_code(CPUSPARCState *env,
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}
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static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
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int *prot, int *access_index,
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int *prot, int *access_index, MemTxAttrs *attrs,
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target_ulong address, int rw, int mmu_idx,
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target_ulong *page_size)
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{
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@ -716,11 +717,11 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
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}
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if (rw == 2) {
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return get_physical_address_code(env, physical, prot, address,
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return get_physical_address_code(env, physical, prot, attrs, address,
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mmu_idx);
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} else {
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return get_physical_address_data(env, physical, prot, address, rw,
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mmu_idx);
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return get_physical_address_data(env, physical, prot, attrs, address,
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rw, mmu_idx);
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}
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}
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@ -734,10 +735,11 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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target_ulong vaddr;
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hwaddr paddr;
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target_ulong page_size;
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MemTxAttrs attrs = {};
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int error_code = 0, prot, access_index;
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address &= TARGET_PAGE_MASK;
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error_code = get_physical_address(env, &paddr, &prot, &access_index,
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error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs,
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address, access_type,
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mmu_idx, &page_size);
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if (likely(error_code == 0)) {
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@ -747,7 +749,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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env->dmmu.mmu_primary_context,
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env->dmmu.mmu_secondary_context);
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tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
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tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx,
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page_size);
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return true;
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}
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if (probe) {
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@ -849,9 +852,10 @@ static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys,
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{
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target_ulong page_size;
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int prot, access_index;
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MemTxAttrs attrs = {};
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return get_physical_address(env, phys, &prot, &access_index, addr, rw,
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mmu_idx, &page_size);
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return get_physical_address(env, phys, &prot, &access_index, &attrs, addr,
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rw, mmu_idx, &page_size);
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}
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#if defined(TARGET_SPARC64)
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