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tcg: Drop union from TCGArgConstraint

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The union is unused; let "regs" appear in the main structure
without the "u.regs" wrapping.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-09-03 15:19:03 -07:00
parent e2e7168a21
commit 9be0d08019
11 changed files with 91 additions and 93 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/tcg/tcg.h
View File

@ -985,9 +985,7 @@ void tcg_dump_op_count(void);
typedef struct TCGArgConstraint {
uint16_t ct;
uint8_t alias_index;
union {
TCGRegSet regs;
} u;
} TCGArgConstraint;
#define TCG_MAX_OP_ARGS 16

14
tcg/aarch64/tcg-target.c.inc
View File

@ -129,22 +129,22 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) {
case 'r': /* general registers */
ct->ct |= TCG_CT_REG;
ct->u.regs |= 0xffffffffu;
ct->regs |= 0xffffffffu;
break;
case 'w': /* advsimd registers */
ct->ct |= TCG_CT_REG;
ct->u.regs |= 0xffffffff00000000ull;
ct->regs |= 0xffffffff00000000ull;
break;
case 'l': /* qemu_ld / qemu_st address, data_reg */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffffu;
ct->regs = 0xffffffffu;
#ifdef CONFIG_SOFTMMU
/* x0 and x1 will be overwritten when reading the tlb entry,
and x2, and x3 for helper args, better to avoid using them. */
tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3);
tcg_regset_reset_reg(ct->regs, TCG_REG_X0);
tcg_regset_reset_reg(ct->regs, TCG_REG_X1);
tcg_regset_reset_reg(ct->regs, TCG_REG_X2);
tcg_regset_reset_reg(ct->regs, TCG_REG_X3);
#endif
break;
case 'A': /* Valid for arithmetic immediate (positive or negative). */

26
tcg/arm/tcg-target.c.inc
View File

@ -254,40 +254,40 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
case 'r':
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffff;
ct->regs = 0xffff;
break;
/* qemu_ld address */
case 'l':
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffff;
ct->regs = 0xffff;
#ifdef CONFIG_SOFTMMU
/* r0-r2,lr will be overwritten when reading the tlb entry,
so don't use these. */
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
#endif
break;
/* qemu_st address & data */
case 's':
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffff;
ct->regs = 0xffff;
/* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
and r0-r1 doing the byte swapping, so don't use these. */
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
#if defined(CONFIG_SOFTMMU)
/* Avoid clashes with registers being used for helper args */
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
#if TARGET_LONG_BITS == 64
/* Avoid clashes with registers being used for helper args */
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#endif
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
#endif
break;

26
tcg/i386/tcg-target.c.inc
View File

@ -209,42 +209,42 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch(*ct_str++) {
case 'a':
ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
break;
case 'b':
ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
break;
case 'c':
ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
break;
case 'd':
ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
break;
case 'S':
ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
break;
case 'D':
ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
break;
case 'q':
/* A register that can be used as a byte operand. */
ct->ct |= TCG_CT_REG;
ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
break;
case 'Q':
/* A register with an addressable second byte (e.g. %ah). */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xf;
ct->regs = 0xf;
break;
case 'r':
/* A general register. */
ct->ct |= TCG_CT_REG;
ct->u.regs |= ALL_GENERAL_REGS;
ct->regs |= ALL_GENERAL_REGS;
break;
case 'W':
/* With TZCNT/LZCNT, we can have operand-size as an input. */
@ -253,15 +253,15 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
case 'x':
/* A vector register. */
ct->ct |= TCG_CT_REG;
ct->u.regs |= ALL_VECTOR_REGS;
ct->regs |= ALL_VECTOR_REGS;
break;
/* qemu_ld/st address constraint */
case 'L':
ct->ct |= TCG_CT_REG;
ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1);
ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
break;
case 'e':

18
tcg/mips/tcg-target.c.inc
View File

@ -196,28 +196,28 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch(*ct_str++) {
case 'r':
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff;
ct->regs = 0xffffffff;
break;
case 'L': /* qemu_ld input arg constraint */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff;
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
#if defined(CONFIG_SOFTMMU)
if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
}
#endif
break;
case 'S': /* qemu_st constraint */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff;
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
#if defined(CONFIG_SOFTMMU)
if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
} else {
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
}
#endif
break;

24
tcg/ppc/tcg-target.c.inc
View File

@ -225,33 +225,33 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) {
case 'A': case 'B': case 'C': case 'D':
ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
break;
case 'r':
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff;
ct->regs = 0xffffffff;
break;
case 'v':
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff00000000ull;
ct->regs = 0xffffffff00000000ull;
break;
case 'L': /* qemu_ld constraint */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff;
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
#endif
break;
case 'S': /* qemu_st constraint */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff;
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
tcg_regset_reset_reg(ct->regs, TCG_REG_R6);
#endif
break;
case 'I':

14
tcg/riscv/tcg-target.c.inc
View File

@ -138,19 +138,19 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) {
case 'r':
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff;
ct->regs = 0xffffffff;
break;
case 'L':
/* qemu_ld/qemu_st constraint */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff;
ct->regs = 0xffffffff;
/* qemu_ld/qemu_st uses TCG_REG_TMP0 */
#if defined(CONFIG_SOFTMMU)
tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]);
tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]);
tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
#endif
break;
case 'I':

18
tcg/s390/tcg-target.c.inc
View File

@ -409,24 +409,24 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) {
case 'r': /* all registers */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffff;
ct->regs = 0xffff;
break;
case 'L': /* qemu_ld/st constraint */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffff;
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
ct->regs = 0xffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
break;
case 'a': /* force R2 for division */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0;
tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);
ct->regs = 0;
tcg_regset_set_reg(ct->regs, TCG_REG_R2);
break;
case 'b': /* force R3 for division */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0;
tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
ct->regs = 0;
tcg_regset_set_reg(ct->regs, TCG_REG_R3);
break;
case 'A':
ct->ct |= TCG_CT_CONST_S33;

16
tcg/sparc/tcg-target.c.inc
View File

@ -326,27 +326,27 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) {
case 'r':
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff;
ct->regs = 0xffffffff;
break;
case 'R':
ct->ct |= TCG_CT_REG;
ct->u.regs = ALL_64;
ct->regs = ALL_64;
break;
case 'A': /* qemu_ld/st address constraint */
ct->ct |= TCG_CT_REG;
ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
reserve_helpers:
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
tcg_regset_reset_reg(ct->regs, TCG_REG_O1);
tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
break;
case 's': /* qemu_st data 32-bit constraint */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff;
ct->regs = 0xffffffff;
goto reserve_helpers;
case 'S': /* qemu_st data 64-bit constraint */
ct->ct |= TCG_CT_REG;
ct->u.regs = ALL_64;
ct->regs = ALL_64;
goto reserve_helpers;
case 'I':
ct->ct |= TCG_CT_CONST_S11;

22
tcg/tcg.c
View File

@ -2210,7 +2210,7 @@ static int get_constraint_priority(const TCGOpDef *def, int k)
return 0;
n = 0;
for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
if (tcg_regset_test_reg(arg_ct->u.regs, i))
if (tcg_regset_test_reg(arg_ct->regs, i))
n++;
}
}
@ -2268,7 +2268,7 @@ static void process_op_defs(TCGContext *s)
/* Incomplete TCGTargetOpDef entry. */
tcg_debug_assert(ct_str != NULL);
def->args_ct[i].u.regs = 0;
def->args_ct[i].regs = 0;
def->args_ct[i].ct = 0;
while (*ct_str != '\0') {
switch(*ct_str) {
@ -2855,13 +2855,13 @@ static void liveness_pass_1(TCGContext *s)
pset = la_temp_pref(ts);
set = *pset;
set &= ct->u.regs;
set &= ct->regs;
if (ct->ct & TCG_CT_IALIAS) {
set &= op->output_pref[ct->alias_index];
}
/* If the combination is not possible, restart. */
if (set == 0) {
set = ct->u.regs;
set = ct->regs;
}
*pset = set;
}
@ -3551,8 +3551,8 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)
return;
}
dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs;
dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].u.regs;
dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs;
dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs;
/* Allocate the output register now. */
if (ots->val_type != TEMP_VAL_REG) {
@ -3706,10 +3706,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
}
}
temp_load(s, ts, arg_ct->u.regs, i_allocated_regs, i_preferred_regs);
temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs);
reg = ts->reg;
if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
if (tcg_regset_test_reg(arg_ct->regs, reg)) {
/* nothing to do : the constraint is satisfied */
} else {
allocate_in_reg:
@ -3717,7 +3717,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
and move the temporary register into it */
temp_load(s, ts, tcg_target_available_regs[ts->type],
i_allocated_regs, 0);
reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs,
reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs,
o_preferred_regs, ts->indirect_base);
if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
/*
@ -3772,11 +3772,11 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
&& !const_args[arg_ct->alias_index]) {
reg = new_args[arg_ct->alias_index];
} else if (arg_ct->ct & TCG_CT_NEWREG) {
reg = tcg_reg_alloc(s, arg_ct->u.regs,
reg = tcg_reg_alloc(s, arg_ct->regs,
i_allocated_regs | o_allocated_regs,
op->output_pref[k], ts->indirect_base);
} else {
reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs,
reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs,
op->output_pref[k], ts->indirect_base);
}
tcg_regset_set_reg(o_allocated_regs, reg);

2
tcg/tci/tcg-target.c.inc
View File

@ -393,7 +393,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
case 'L': /* qemu_ld constraint */
case 'S': /* qemu_st constraint */
ct->ct |= TCG_CT_REG;
ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1;
ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
break;
default:
return NULL;