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target-tricore: fix msub32_q producing the wrong overflow bit

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The inversion of the overflow bit as a special case, which was needed for the
madd32_q instructions, does not apply for msub32_q instructions. So remove it.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <1432289758-6250-3-git-send-email-kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2015-05-22 12:15:57 +02:00
parent 05b6ca9bbc
commit 9bbd4843c0
1 changed files with 0 additions and 11 deletions
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11
target-tricore/translate.c
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@ -1980,17 +1980,6 @@ gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
tcg_gen_or_i64(t1, t1, t2);
tcg_gen_trunc_i64_i32(cpu_PSW_V, t1);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* We produce an overflow on the host if the mul before was
(0x80000000 * 0x80000000) << 1). If this is the
case, we negate the ovf. */
if (n == 1) {
tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
tcg_gen_and_tl(temp, temp, temp2);
tcg_gen_shli_tl(temp, temp, 31);
/* negate v bit, if special condition */
tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
}
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */