target/arm: A32, T32: Create Instruction Syndromes for Data Aborts
Add support for generating the ISS (Instruction Specific Syndrome)
for Data Abort exceptions taken from AArch32. These syndromes are
used by hypervisors for example to trap and emulate memory accesses.
This is the equivalent for AArch32 guests of the work done for AArch64
guests in commit aaa1f954d4.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Peter Maydell
parent
63f26fcfda
commit
9bb6558a21
@ -379,20 +379,6 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
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}
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}
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static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
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{
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/* We don't need to save all of the syndrome so we mask and shift
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* out uneeded bits to help the sleb128 encoder do a better job.
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*/
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syn &= ARM_INSN_START_WORD2_MASK;
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syn >>= ARM_INSN_START_WORD2_SHIFT;
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/* We check and clear insn_start_idx to catch multiple updates. */
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assert(s->insn_start_idx != 0);
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tcg_set_insn_param(s->insn_start_idx, 2, syn);
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s->insn_start_idx = 0;
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}
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static void unallocated_encoding(DisasContext *s)
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{
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/* Unallocated and reserved encodings are uncategorized */
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@ -102,6 +102,49 @@ void arm_translate_init(void)
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a64_translate_init();
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}
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/* Flags for the disas_set_da_iss info argument:
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* lower bits hold the Rt register number, higher bits are flags.
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*/
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typedef enum ISSInfo {
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ISSNone = 0,
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ISSRegMask = 0x1f,
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ISSInvalid = (1 << 5),
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ISSIsAcqRel = (1 << 6),
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ISSIsWrite = (1 << 7),
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ISSIs16Bit = (1 << 8),
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} ISSInfo;
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/* Save the syndrome information for a Data Abort */
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static void disas_set_da_iss(DisasContext *s, TCGMemOp memop, ISSInfo issinfo)
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{
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uint32_t syn;
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int sas = memop & MO_SIZE;
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bool sse = memop & MO_SIGN;
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bool is_acqrel = issinfo & ISSIsAcqRel;
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bool is_write = issinfo & ISSIsWrite;
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bool is_16bit = issinfo & ISSIs16Bit;
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int srt = issinfo & ISSRegMask;
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if (issinfo & ISSInvalid) {
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/* Some callsites want to conditionally provide ISS info,
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* eg "only if this was not a writeback"
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*/
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return;
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}
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if (srt == 15) {
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/* For AArch32, insns where the src/dest is R15 never generate
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* ISS information. Catching that here saves checking at all
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* the call sites.
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*/
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return;
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}
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syn = syn_data_abort_with_iss(0, sas, sse, srt, 0, is_acqrel,
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0, 0, 0, is_write, 0, is_16bit);
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disas_set_insn_syndrome(s, syn);
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}
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static inline ARMMMUIdx get_a32_user_mem_index(DisasContext *s)
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{
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/* Return the mmu_idx to use for A32/T32 "unprivileged load/store"
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@ -933,6 +976,14 @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
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TCGv_i32 a32, int index) \
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{ \
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gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \
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} \
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static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \
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TCGv_i32 val, \
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TCGv_i32 a32, int index, \
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ISSInfo issinfo) \
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{ \
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gen_aa32_ld##SUFF(s, val, a32, index); \
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disas_set_da_iss(s, OPC, issinfo); \
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}
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#define DO_GEN_ST(SUFF, OPC) \
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@ -940,6 +991,14 @@ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
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TCGv_i32 a32, int index) \
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{ \
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gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \
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} \
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static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \
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TCGv_i32 val, \
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TCGv_i32 a32, int index, \
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ISSInfo issinfo) \
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{ \
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gen_aa32_st##SUFF(s, val, a32, index); \
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disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \
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}
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static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
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@ -8682,16 +8741,19 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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tmp = tcg_temp_new_i32();
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switch (op1) {
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case 0: /* lda */
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gen_aa32_ld32u(s, tmp, addr,
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get_mem_index(s));
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gen_aa32_ld32u_iss(s, tmp, addr,
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get_mem_index(s),
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rd | ISSIsAcqRel);
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break;
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case 2: /* ldab */
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gen_aa32_ld8u(s, tmp, addr,
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get_mem_index(s));
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gen_aa32_ld8u_iss(s, tmp, addr,
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get_mem_index(s),
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rd | ISSIsAcqRel);
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break;
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case 3: /* ldah */
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gen_aa32_ld16u(s, tmp, addr,
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get_mem_index(s));
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gen_aa32_ld16u_iss(s, tmp, addr,
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get_mem_index(s),
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rd | ISSIsAcqRel);
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break;
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default:
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abort();
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@ -8702,16 +8764,19 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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tmp = load_reg(s, rm);
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switch (op1) {
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case 0: /* stl */
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gen_aa32_st32(s, tmp, addr,
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get_mem_index(s));
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gen_aa32_st32_iss(s, tmp, addr,
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get_mem_index(s),
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rm | ISSIsAcqRel);
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break;
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case 2: /* stlb */
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gen_aa32_st8(s, tmp, addr,
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get_mem_index(s));
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gen_aa32_st8_iss(s, tmp, addr,
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get_mem_index(s),
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rm | ISSIsAcqRel);
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break;
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case 3: /* stlh */
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gen_aa32_st16(s, tmp, addr,
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get_mem_index(s));
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gen_aa32_st16_iss(s, tmp, addr,
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get_mem_index(s),
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rm | ISSIsAcqRel);
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break;
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default:
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abort();
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@ -8785,10 +8850,15 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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bool wbit = insn & (1 << 21);
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bool pbit = insn & (1 << 24);
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bool doubleword = false;
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ISSInfo issinfo;
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/* Misc load/store */
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rn = (insn >> 16) & 0xf;
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rd = (insn >> 12) & 0xf;
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/* ISS not valid if writeback */
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issinfo = (pbit & !wbit) ? rd : ISSInvalid;
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if (!load && (sh & 2)) {
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/* doubleword */
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ARCH(5TE);
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@ -8832,20 +8902,23 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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tmp = tcg_temp_new_i32();
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switch (sh) {
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case 1:
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gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
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gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s),
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issinfo);
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break;
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case 2:
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gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));
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gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s),
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issinfo);
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break;
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default:
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case 3:
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gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));
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gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s),
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issinfo);
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break;
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}
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} else {
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/* store */
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tmp = load_reg(s, rd);
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gen_aa32_st16(s, tmp, addr, get_mem_index(s));
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gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), issinfo);
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tcg_temp_free_i32(tmp);
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}
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/* Perform base writeback before the loaded value to
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@ -9198,17 +9271,17 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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/* load */
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tmp = tcg_temp_new_i32();
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if (insn & (1 << 22)) {
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gen_aa32_ld8u(s, tmp, tmp2, i);
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gen_aa32_ld8u_iss(s, tmp, tmp2, i, rd);
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} else {
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gen_aa32_ld32u(s, tmp, tmp2, i);
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gen_aa32_ld32u_iss(s, tmp, tmp2, i, rd);
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}
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} else {
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/* store */
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tmp = load_reg(s, rd);
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if (insn & (1 << 22)) {
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gen_aa32_st8(s, tmp, tmp2, i);
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gen_aa32_st8_iss(s, tmp, tmp2, i, rd);
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} else {
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gen_aa32_st32(s, tmp, tmp2, i);
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gen_aa32_st32_iss(s, tmp, tmp2, i, rd);
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}
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tcg_temp_free_i32(tmp);
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}
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@ -9669,13 +9742,16 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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tmp = tcg_temp_new_i32();
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switch (op) {
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case 0: /* ldab */
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gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
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gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s),
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rs | ISSIsAcqRel);
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break;
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case 1: /* ldah */
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gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
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gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s),
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rs | ISSIsAcqRel);
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break;
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case 2: /* lda */
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gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
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gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
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rs | ISSIsAcqRel);
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break;
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default:
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abort();
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@ -9685,13 +9761,16 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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tmp = load_reg(s, rs);
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switch (op) {
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case 0: /* stlb */
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gen_aa32_st8(s, tmp, addr, get_mem_index(s));
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gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s),
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rs | ISSIsAcqRel);
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break;
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case 1: /* stlh */
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gen_aa32_st16(s, tmp, addr, get_mem_index(s));
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gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s),
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rs | ISSIsAcqRel);
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break;
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case 2: /* stl */
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gen_aa32_st32(s, tmp, addr, get_mem_index(s));
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gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s),
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rs | ISSIsAcqRel);
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break;
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default:
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abort();
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@ -10637,6 +10716,8 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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int postinc = 0;
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int writeback = 0;
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int memidx;
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ISSInfo issinfo;
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if ((insn & 0x01100000) == 0x01000000) {
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if (disas_neon_ls_insn(s, insn)) {
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goto illegal_op;
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@ -10740,24 +10821,27 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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}
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}
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}
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issinfo = writeback ? ISSInvalid : rs;
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if (insn & (1 << 20)) {
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/* Load. */
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tmp = tcg_temp_new_i32();
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switch (op) {
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case 0:
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gen_aa32_ld8u(s, tmp, addr, memidx);
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gen_aa32_ld8u_iss(s, tmp, addr, memidx, issinfo);
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break;
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case 4:
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gen_aa32_ld8s(s, tmp, addr, memidx);
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gen_aa32_ld8s_iss(s, tmp, addr, memidx, issinfo);
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break;
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case 1:
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gen_aa32_ld16u(s, tmp, addr, memidx);
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gen_aa32_ld16u_iss(s, tmp, addr, memidx, issinfo);
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break;
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case 5:
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gen_aa32_ld16s(s, tmp, addr, memidx);
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gen_aa32_ld16s_iss(s, tmp, addr, memidx, issinfo);
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break;
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case 2:
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gen_aa32_ld32u(s, tmp, addr, memidx);
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gen_aa32_ld32u_iss(s, tmp, addr, memidx, issinfo);
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break;
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default:
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tcg_temp_free_i32(tmp);
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@ -10774,13 +10858,13 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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tmp = load_reg(s, rs);
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switch (op) {
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case 0:
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gen_aa32_st8(s, tmp, addr, memidx);
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gen_aa32_st8_iss(s, tmp, addr, memidx, issinfo);
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break;
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case 1:
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gen_aa32_st16(s, tmp, addr, memidx);
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gen_aa32_st16_iss(s, tmp, addr, memidx, issinfo);
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break;
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case 2:
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gen_aa32_st32(s, tmp, addr, memidx);
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gen_aa32_st32_iss(s, tmp, addr, memidx, issinfo);
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break;
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default:
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tcg_temp_free_i32(tmp);
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@ -10917,7 +11001,8 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
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addr = tcg_temp_new_i32();
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tcg_gen_movi_i32(addr, val);
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tmp = tcg_temp_new_i32();
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gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
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gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
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rd | ISSIs16Bit);
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tcg_temp_free_i32(addr);
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store_reg(s, rd, tmp);
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break;
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@ -11120,28 +11205,28 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
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switch (op) {
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case 0: /* str */
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gen_aa32_st32(s, tmp, addr, get_mem_index(s));
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gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
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break;
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case 1: /* strh */
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gen_aa32_st16(s, tmp, addr, get_mem_index(s));
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gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
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break;
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case 2: /* strb */
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gen_aa32_st8(s, tmp, addr, get_mem_index(s));
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gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
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break;
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case 3: /* ldrsb */
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gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));
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gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
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break;
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case 4: /* ldr */
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gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
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gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
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break;
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case 5: /* ldrh */
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gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
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gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
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break;
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case 6: /* ldrb */
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gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
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gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
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break;
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case 7: /* ldrsh */
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gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));
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gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
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break;
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}
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if (op >= 3) { /* load */
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@ -11185,12 +11270,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
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if (insn & (1 << 11)) {
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/* load */
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tmp = tcg_temp_new_i32();
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gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
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gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
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store_reg(s, rd, tmp);
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} else {
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/* store */
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tmp = load_reg(s, rd);
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gen_aa32_st8(s, tmp, addr, get_mem_index(s));
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gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
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tcg_temp_free_i32(tmp);
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}
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tcg_temp_free_i32(addr);
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@ -11207,12 +11292,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
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if (insn & (1 << 11)) {
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/* load */
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tmp = tcg_temp_new_i32();
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gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
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gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
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store_reg(s, rd, tmp);
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} else {
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/* store */
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tmp = load_reg(s, rd);
|
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gen_aa32_st16(s, tmp, addr, get_mem_index(s));
|
||||
gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
|
||||
tcg_temp_free_i32(tmp);
|
||||
}
|
||||
tcg_temp_free_i32(addr);
|
||||
@ -11228,12 +11313,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
|
||||
if (insn & (1 << 11)) {
|
||||
/* load */
|
||||
tmp = tcg_temp_new_i32();
|
||||
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
|
||||
gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
|
||||
store_reg(s, rd, tmp);
|
||||
} else {
|
||||
/* store */
|
||||
tmp = load_reg(s, rd);
|
||||
gen_aa32_st32(s, tmp, addr, get_mem_index(s));
|
||||
gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
|
||||
tcg_temp_free_i32(tmp);
|
||||
}
|
||||
tcg_temp_free_i32(addr);
|
||||
@ -11715,6 +11800,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
|
||||
store_cpu_field(tmp, condexec_bits);
|
||||
}
|
||||
do {
|
||||
dc->insn_start_idx = tcg_op_buf_count();
|
||||
tcg_gen_insn_start(dc->pc,
|
||||
(dc->condexec_cond << 4) | (dc->condexec_mask >> 1),
|
||||
0);
|
||||
|
||||
@ -104,6 +104,20 @@ static inline int default_exception_el(DisasContext *s)
|
||||
? 3 : MAX(1, s->current_el);
|
||||
}
|
||||
|
||||
static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
|
||||
{
|
||||
/* We don't need to save all of the syndrome so we mask and shift
|
||||
* out unneeded bits to help the sleb128 encoder do a better job.
|
||||
*/
|
||||
syn &= ARM_INSN_START_WORD2_MASK;
|
||||
syn >>= ARM_INSN_START_WORD2_SHIFT;
|
||||
|
||||
/* We check and clear insn_start_idx to catch multiple updates. */
|
||||
assert(s->insn_start_idx != 0);
|
||||
tcg_set_insn_param(s->insn_start_idx, 2, syn);
|
||||
s->insn_start_idx = 0;
|
||||
}
|
||||
|
||||
/* target-specific extra values for is_jmp */
|
||||
/* These instructions trap after executing, so the A32/T32 decoder must
|
||||
* defer them until after the conditional execution state has been updated.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user