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tcg: Add logical simplifications during gvec expand

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We handle many of these during integer expansion, and the
rest of them during integer optimization.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2018-12-17 12:54:53 -08:00
parent ad7a21e812
commit 9a9eda78e4
1 changed files with 30 additions and 5 deletions
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25
tcg/tcg-op-gvec.c
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@ -1840,7 +1840,12 @@ void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs,
.opc = INDEX_op_and_vec, .opc = INDEX_op_and_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64, .prefer_i64 = TCG_TARGET_REG_BITS == 64,
}; };
if (aofs == bofs) {
tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
} else {
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
}
} }
void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs,
@ -1853,7 +1858,12 @@ void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs,
.opc = INDEX_op_or_vec, .opc = INDEX_op_or_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64, .prefer_i64 = TCG_TARGET_REG_BITS == 64,
}; };
if (aofs == bofs) {
tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
} else {
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
}
} }
void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs,
@ -1866,7 +1876,12 @@ void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs,
.opc = INDEX_op_xor_vec, .opc = INDEX_op_xor_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64, .prefer_i64 = TCG_TARGET_REG_BITS == 64,
}; };
if (aofs == bofs) {
tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0);
} else {
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
}
} }
void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
@ -1879,7 +1894,12 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
.opc = INDEX_op_andc_vec, .opc = INDEX_op_andc_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64, .prefer_i64 = TCG_TARGET_REG_BITS == 64,
}; };
if (aofs == bofs) {
tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0);
} else {
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
}
} }
void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
@ -1892,7 +1912,12 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
.opc = INDEX_op_orc_vec, .opc = INDEX_op_orc_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64, .prefer_i64 = TCG_TARGET_REG_BITS == 64,
}; };
if (aofs == bofs) {
tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, -1);
} else {
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
}
} }
static const GVecGen2s gop_ands = { static const GVecGen2s gop_ands = {