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aspeed queue:

Browse Source 
* Fixed eMMC size calculation
 * Fixed IRQ definitions on AST2700
 * Added RTC support to AST2700
 * Fixed timer IRQ status on AST2600
 * Improved SDHCI model with new registers
 * Added -nodefaults support to AST1030
 * Provided a way to use an eMMC device without boot partitions
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Merge tag 'pull-aspeed-20241104' of https://github.com/legoater/qemu into staging

aspeed queue:

* Fixed eMMC size calculation
* Fixed IRQ definitions on AST2700
* Added RTC support to AST2700
* Fixed timer IRQ status on AST2600
* Improved SDHCI model with new registers
* Added -nodefaults support to AST1030
* Provided a way to use an eMMC device without boot partitions

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# gpg: Signature made Mon 04 Nov 2024 10:35:54 GMT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full]
# gpg:                 aka "Cédric Le Goater <clg@kaod.org>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20241104' of https://github.com/legoater/qemu:
  aspeed: Don't set always boot properties of the emmc device
  aspeed: Support create flash devices via command line for AST1030
  hw/sd/aspeed_sdhci: Introduce Capabilities Register 2 for SD slot 0 and 1
  hw/timer/aspeed: Fix interrupt status does not be cleared for AST2600
  hw/timer/aspeed: Fix coding style
  aspeed/soc: Support RTC for AST2700
  hw/arm/aspeed_ast27x0: Avoid hardcoded '256' in IRQ calculation
  hw/arm/aspeed_ast27x0: Use bsa.h for PPI definitions
  hw/sd/sdcard: Fix calculation of size when using eMMC boot partitions
  hw/arm: enable at24c with aspeed

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-11-05 10:06:08 +00:00
commit 9a7b0a8618
6 changed files with 89 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
hw/arm/Kconfig
View File

@ -539,6 +539,7 @@ config ASPEED_SOC
select PMBUS select PMBUS
select MAX31785 select MAX31785
select FSI_APB2OPB_ASPEED select FSI_APB2OPB_ASPEED
select AT24C
config MPS2 config MPS2
bool bool

38
hw/arm/aspeed.c
View File

@ -338,10 +338,20 @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc,
return; return;
} }
card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD);
if (emmc) {
/*
* Force the boot properties of the eMMC device only when the
* machine is strapped to boot from eMMC. Without these
* settings, the machine would not boot.
*
* This also allows the machine to use an eMMC device without
* boot areas when booting from the flash device (or -kernel)
* Ideally, the device and its properties should be defined on
* the command line.
*/
if (emmc && boot_emmc) {
qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB); qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB);
qdev_prop_set_uint8(card, "boot-config", qdev_prop_set_uint8(card, "boot-config", 0x1 << 3);
boot_emmc ? 0x1 << 3 : 0x0);
} }
qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal); &error_fatal);
@ -1594,18 +1604,20 @@ static void aspeed_minibmc_machine_init(MachineState *machine)
connect_serial_hds_to_uarts(bmc); connect_serial_hds_to_uarts(bmc);
qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
aspeed_board_init_flashes(&bmc->soc->fmc, if (defaults_enabled()) {
bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, aspeed_board_init_flashes(&bmc->soc->fmc,
amc->num_cs, bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
0); amc->num_cs,
0);
aspeed_board_init_flashes(&bmc->soc->spi[0], aspeed_board_init_flashes(&bmc->soc->spi[0],
bmc->spi_model ? bmc->spi_model : amc->spi_model, bmc->spi_model ? bmc->spi_model : amc->spi_model,
amc->num_cs, amc->num_cs); amc->num_cs, amc->num_cs);
aspeed_board_init_flashes(&bmc->soc->spi[1], aspeed_board_init_flashes(&bmc->soc->spi[1],
bmc->spi_model ? bmc->spi_model : amc->spi_model, bmc->spi_model ? bmc->spi_model : amc->spi_model,
amc->num_cs, (amc->num_cs * 2)); amc->num_cs, (amc->num_cs * 2));
}
if (amc->i2c_init) { if (amc->i2c_init) {
amc->i2c_init(bmc); amc->i2c_init(bmc);

33
hw/arm/aspeed_ast27x0.c
View File

@ -13,6 +13,7 @@
#include "qapi/error.h" #include "qapi/error.h"
#include "hw/misc/unimp.h" #include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h" #include "hw/arm/aspeed_soc.h"
#include "hw/arm/bsa.h"
#include "qemu/module.h" #include "qemu/module.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "hw/i2c/aspeed_i2c.h" #include "hw/i2c/aspeed_i2c.h"
@ -63,9 +64,10 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_ADC] = 0x14C00000, [ASPEED_DEV_ADC] = 0x14C00000,
[ASPEED_DEV_I2C] = 0x14C0F000, [ASPEED_DEV_I2C] = 0x14C0F000,
[ASPEED_DEV_GPIO] = 0x14C0B000, [ASPEED_DEV_GPIO] = 0x14C0B000,
[ASPEED_DEV_RTC] = 0x12C0F000,
}; };
#define AST2700_MAX_IRQ 288 #define AST2700_MAX_IRQ 256
/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
static const int aspeed_soc_ast2700_irqmap[] = { static const int aspeed_soc_ast2700_irqmap[] = {
@ -376,6 +378,8 @@ static void aspeed_soc_ast2700_init(Object *obj)
snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
object_initialize_child(obj, "gpio", &s->gpio, typename); object_initialize_child(obj, "gpio", &s->gpio, typename);
object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
} }
/* /*
@ -402,7 +406,7 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
gicdev = DEVICE(&a->gic); gicdev = DEVICE(&a->gic);
qdev_prop_set_uint32(gicdev, "revision", 3); qdev_prop_set_uint32(gicdev, "revision", 3);
qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus);
qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ); qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL);
redist_region_count = qlist_new(); redist_region_count = qlist_new();
qlist_append_int(redist_region_count, sc->num_cpus); qlist_append_int(redist_region_count, sc->num_cpus);
@ -416,28 +420,27 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
for (i = 0; i < sc->num_cpus; i++) { for (i = 0; i < sc->num_cpus; i++) {
DeviceState *cpudev = DEVICE(&a->cpu[i]); DeviceState *cpudev = DEVICE(&a->cpu[i]);
int NUM_IRQS = 256, ARCH_GIC_MAINT_IRQ = 9, VIRTUAL_PMU_IRQ = 7; int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL;
int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
const int timer_irq[] = { const int timer_irq[] = {
[GTIMER_PHYS] = 14, [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
[GTIMER_VIRT] = 11, [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
[GTIMER_HYP] = 10, [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
[GTIMER_SEC] = 13, [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
}; };
int j; int j;
for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { for (j = 0; j < ARRAY_SIZE(timer_irq); j++) {
qdev_connect_gpio_out(cpudev, j, qdev_connect_gpio_out(cpudev, j,
qdev_get_gpio_in(gicdev, ppibase + timer_irq[j])); qdev_get_gpio_in(gicdev, intidbase + timer_irq[j]));
} }
qemu_irq irq = qdev_get_gpio_in(gicdev, qemu_irq irq = qdev_get_gpio_in(gicdev,
ppibase + ARCH_GIC_MAINT_IRQ); intidbase + ARCH_GIC_MAINT_IRQ);
qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
0, irq); 0, irq);
qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
qdev_get_gpio_in(gicdev, ppibase + VIRTUAL_PMU_IRQ)); qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ));
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
sysbus_connect_irq(gicbusdev, i + sc->num_cpus, sysbus_connect_irq(gicbusdev, i + sc->num_cpus,
@ -670,6 +673,14 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
/* RTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
return;
}
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);

40
hw/sd/aspeed_sdhci.c
View File

@ -24,8 +24,10 @@
#define ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005 #define ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005
#define ASPEED_SDHCI_BUS 0x08 #define ASPEED_SDHCI_BUS 0x08
#define ASPEED_SDHCI_SDIO_140 0x10 #define ASPEED_SDHCI_SDIO_140 0x10
#define ASPEED_SDHCI_SDIO_144 0x14
#define ASPEED_SDHCI_SDIO_148 0x18 #define ASPEED_SDHCI_SDIO_148 0x18
#define ASPEED_SDHCI_SDIO_240 0x20 #define ASPEED_SDHCI_SDIO_240 0x20
#define ASPEED_SDHCI_SDIO_244 0x24
#define ASPEED_SDHCI_SDIO_248 0x28 #define ASPEED_SDHCI_SDIO_248 0x28
#define ASPEED_SDHCI_WP_POL 0xec #define ASPEED_SDHCI_WP_POL 0xec
#define ASPEED_SDHCI_CARD_DET 0xf0 #define ASPEED_SDHCI_CARD_DET 0xf0
@ -35,21 +37,27 @@
static uint64_t aspeed_sdhci_read(void *opaque, hwaddr addr, unsigned int size) static uint64_t aspeed_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
{ {
uint32_t val = 0; uint64_t val = 0;
AspeedSDHCIState *sdhci = opaque; AspeedSDHCIState *sdhci = opaque;
switch (addr) { switch (addr) {
case ASPEED_SDHCI_SDIO_140: case ASPEED_SDHCI_SDIO_140:
val = (uint32_t)sdhci->slots[0].capareg; val = extract64(sdhci->slots[0].capareg, 0, 32);
break;
case ASPEED_SDHCI_SDIO_144:
val = extract64(sdhci->slots[0].capareg, 32, 32);
break; break;
case ASPEED_SDHCI_SDIO_148: case ASPEED_SDHCI_SDIO_148:
val = (uint32_t)sdhci->slots[0].maxcurr; val = extract64(sdhci->slots[0].maxcurr, 0, 32);
break; break;
case ASPEED_SDHCI_SDIO_240: case ASPEED_SDHCI_SDIO_240:
val = (uint32_t)sdhci->slots[1].capareg; val = extract64(sdhci->slots[1].capareg, 0, 32);
break;
case ASPEED_SDHCI_SDIO_244:
val = extract64(sdhci->slots[1].capareg, 32, 32);
break; break;
case ASPEED_SDHCI_SDIO_248: case ASPEED_SDHCI_SDIO_248:
val = (uint32_t)sdhci->slots[1].maxcurr; val = extract64(sdhci->slots[1].maxcurr, 0, 32);
break; break;
default: default:
if (addr < ASPEED_SDHCI_REG_SIZE) { if (addr < ASPEED_SDHCI_REG_SIZE) {
@ -61,9 +69,9 @@ static uint64_t aspeed_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
} }
} }
trace_aspeed_sdhci_read(addr, size, (uint64_t) val); trace_aspeed_sdhci_read(addr, size, val);
return (uint64_t)val; return val;
} }
static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val, static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
@ -79,16 +87,26 @@ static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
sdhci->regs[TO_REG(addr)] = (uint32_t)val & ~ASPEED_SDHCI_INFO_RESET; sdhci->regs[TO_REG(addr)] = (uint32_t)val & ~ASPEED_SDHCI_INFO_RESET;
break; break;
case ASPEED_SDHCI_SDIO_140: case ASPEED_SDHCI_SDIO_140:
sdhci->slots[0].capareg = (uint64_t)(uint32_t)val; sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg, 0, 32, val);
break;
case ASPEED_SDHCI_SDIO_144:
sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg, 32, 32, val);
break; break;
case ASPEED_SDHCI_SDIO_148: case ASPEED_SDHCI_SDIO_148:
sdhci->slots[0].maxcurr = (uint64_t)(uint32_t)val; sdhci->slots[0].maxcurr = deposit64(sdhci->slots[0].maxcurr,
0, 32, val);
break; break;
case ASPEED_SDHCI_SDIO_240: case ASPEED_SDHCI_SDIO_240:
sdhci->slots[1].capareg = (uint64_t)(uint32_t)val; sdhci->slots[1].capareg = deposit64(sdhci->slots[1].capareg,
0, 32, val);
break;
case ASPEED_SDHCI_SDIO_244:
sdhci->slots[1].capareg = deposit64(sdhci->slots[1].capareg,
32, 32, val);
break; break;
case ASPEED_SDHCI_SDIO_248: case ASPEED_SDHCI_SDIO_248:
sdhci->slots[1].maxcurr = (uint64_t)(uint32_t)val; sdhci->slots[1].maxcurr = deposit64(sdhci->slots[0].maxcurr,
0, 32, val);
break; break;
default: default:
if (addr < ASPEED_SDHCI_REG_SIZE) { if (addr < ASPEED_SDHCI_REG_SIZE) {

4
hw/sd/sd.c
View File

@ -834,7 +834,9 @@ static void sd_reset(DeviceState *dev)
sect = 0; sect = 0;
} }
size = sect << HWBLOCK_SHIFT; size = sect << HWBLOCK_SHIFT;
size -= sd_bootpart_offset(sd); if (sd_is_emmc(sd)) {
size -= sd->boot_part_size * 2;
}
sect = sd_addr_to_wpnum(size) + 1; sect = sd_addr_to_wpnum(size) + 1;

15
hw/timer/aspeed_timer.c
View File

@ -276,7 +276,8 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
old_reload = t->reload; old_reload = t->reload;
t->reload = calculate_min_ticks(t, value); t->reload = calculate_min_ticks(t, value);
/* If the reload value was not previously set, or zero, and /*
* If the reload value was not previously set, or zero, and
* the current value is valid, try to start the timer if it is * the current value is valid, try to start the timer if it is
* enabled. * enabled.
*/ */
@ -312,7 +313,8 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
} }
} }
/* Control register operations are broken out into helpers that can be /*
* Control register operations are broken out into helpers that can be
* explicitly called on aspeed_timer_reset(), but also from * explicitly called on aspeed_timer_reset(), but also from
* aspeed_timer_ctrl_op(). * aspeed_timer_ctrl_op().
*/ */
@ -396,7 +398,8 @@ static void aspeed_timer_set_ctrl(AspeedTimerCtrlState *s, uint32_t reg)
AspeedTimer *t; AspeedTimer *t;
const uint8_t enable_mask = BIT(op_enable); const uint8_t enable_mask = BIT(op_enable);
/* Handle a dependency between the 'enable' and remaining three /*
* Handle a dependency between the 'enable' and remaining three
* configuration bits - i.e. if more than one bit in the control set has * configuration bits - i.e. if more than one bit in the control set has
* changed, including the 'enable' bit, then we want either disable the * changed, including the 'enable' bit, then we want either disable the
* timer and perform configuration, or perform configuration and then * timer and perform configuration, or perform configuration and then
@ -577,12 +580,11 @@ static void aspeed_2600_timer_write(AspeedTimerCtrlState *s, hwaddr offset,
switch (offset) { switch (offset) {
case 0x34: case 0x34:
s->irq_sts &= tv; s->irq_sts &= ~tv;
break; break;
case 0x3C: case 0x3C:
aspeed_timer_set_ctrl(s, s->ctrl & ~tv); aspeed_timer_set_ctrl(s, s->ctrl & ~tv);
break; break;
case 0x38: case 0x38:
default: default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
@ -623,7 +625,8 @@ static void aspeed_timer_reset(DeviceState *dev)
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
AspeedTimer *t = &s->timers[i]; AspeedTimer *t = &s->timers[i];
/* Explicitly call helpers to avoid any conditional behaviour through /*
* Explicitly call helpers to avoid any conditional behaviour through
* aspeed_timer_set_ctrl(). * aspeed_timer_set_ctrl().
*/ */
aspeed_timer_ctrl_enable(t, false); aspeed_timer_ctrl_enable(t, false);